Built-in self-test for system-on-chip: a case study

Stroud, Charles E.; Sunwoo, John; Garimella, S.; Harris, Jonathan

doi:10.1109/test.2004.1387347

Cited by 9 publications

(4 citation statements)

References 16 publications

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“…These structures can be implemented in Field Programmable Gate Arrays (FPGA) [5], Application Specific Integrated Circuit (ASIC), System-on-Chip (SOC), which consist of many virtual Intellectual Property modules (IP Core). For SOC, the STP structures can also link IP modules [6].…”

Section: Introductionmentioning

confidence: 99%

Genetic algorithm as self-test path and circular self-test path design method

Chodacki

2018

Vietnam J Comput Sci

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The paper presents the use of Genetic Algorithm to search for non-linear Autonomous Test Structures (ATS) in Built-In Testing approach. Such structures can include essentially STP and CSTP and their modifications. Non-linear structures are more difficult to analyze than the widely used structures such as independent Test Pattern Generator and the Test Response Compactor realized by Linear Feedback Shift Registers. To reduce time-consuming test simulation of sequential circuit, it was used an approach based on the stochastic model of pseudo-random testing. The use of stochastic model significantly affects the time effectiveness of the search for evolutionary autonomous structures. In test simulation procedure, the block of sequential circuit memory is not disconnected. This approach does not require a special selection of memory registers such as BILBOs. A series of studies to test circuits set ISCAS'89 are made. The results of the study are very promising.

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Section: Introductionmentioning

confidence: 99%

Genetic algorithm as self-test path and circular self-test path design method

Chodacki

2018

Vietnam J Comput Sci

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“…A number of BIST approaches have been developed to test the programmable logic and routing resources in FPGAs and embedded FPGA cores in SoCs [1]- [7]. The basic technique is to configure some of the programmable logic blocks (PLBs) in the FPGA core as Test Pattern Generators (TPGs) and Output Response Analyzers (ORAs).…”

Section: Background and Motivationmentioning

confidence: 99%

“…In logic BIST, the BUTs and ORAs are arranged in alternating columns (or rows) and two or more identical TPGs are used to drive the alternating columns (or rows) of BUTs as illustrated in Figure 1 [1]- [3] [7]. The output responses of identically programmed BUTs are compared by ORAs in neighboring columns (or rows).…”

Section: Background and Motivationmentioning

confidence: 99%

“…This implies that the I/O buffers should be tested to ensure the fault-free operation in the same manner as the programmable logic and interconnect resources in the FPGA core are being tested. While a number of Built-In Self-Test (BIST) approaches have been developed for the programmable logic and routing resources in the FPGA core [1]- [7], they have neglected testing the I/O buffers and their associated routing resources.…”

Section: Introductionmentioning

confidence: 99%

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