2004 International Conferce on Test
DOI: 10.1109/test.2004.1387347
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Built-in self-test for system-on-chip: a case study

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Cited by 9 publications
(4 citation statements)
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“…These structures can be implemented in Field Programmable Gate Arrays (FPGA) [5], Application Specific Integrated Circuit (ASIC), System-on-Chip (SOC), which consist of many virtual Intellectual Property modules (IP Core). For SOC, the STP structures can also link IP modules [6].…”
Section: Introductionmentioning
confidence: 99%
“…These structures can be implemented in Field Programmable Gate Arrays (FPGA) [5], Application Specific Integrated Circuit (ASIC), System-on-Chip (SOC), which consist of many virtual Intellectual Property modules (IP Core). For SOC, the STP structures can also link IP modules [6].…”
Section: Introductionmentioning
confidence: 99%
“…A number of BIST approaches have been developed to test the programmable logic and routing resources in FPGAs and embedded FPGA cores in SoCs [1]- [7]. The basic technique is to configure some of the programmable logic blocks (PLBs) in the FPGA core as Test Pattern Generators (TPGs) and Output Response Analyzers (ORAs).…”
Section: Background and Motivationmentioning
confidence: 99%
“…In logic BIST, the BUTs and ORAs are arranged in alternating columns (or rows) and two or more identical TPGs are used to drive the alternating columns (or rows) of BUTs as illustrated in Figure 1 [1]- [3] [7]. The output responses of identically programmed BUTs are compared by ORAs in neighboring columns (or rows).…”
Section: Background and Motivationmentioning
confidence: 99%
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