Genetic Algorithm for Self-Test Path and Circular Self-Test Path Design

Chodacki, Miłosław

doi:10.1007/978-3-319-54430-4_39

Cited by 2 publications

(4 citation statements)

References 11 publications

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“…Every individual has to be simulated and this process is a great time-consuming task. In [7], the stochastic model of pseudo-random testing, which significantly reduces this problem, was described. Using the stochastic model, the simulation of each solution is well reduced due to the conversion of exploration FC in search of a suitable length of sequence.…”

Section: Genetic Algorithm As Nlfsr Design Methodsmentioning

confidence: 99%

“…It should be noted that both in linear and non-linear testing techniques, the circuit MM is typically included into self-testing structure registers as results from ability to improve testability and application of Design for Testability (DFT). An important observations was made in [7].…”

Section: Introductionmentioning

confidence: 99%

“…The paper is an extended version of a previously published article titled "Genetic Algorithm for Self-Test Path and Circular Self-Test Path Design" that was presented at ACIIDS 2017 conference [7].…”

Section: Introductionmentioning

confidence: 99%

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Genetic algorithm as self-test path and circular self-test path design method

Chodacki

2018

Vietnam J Comput Sci

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The paper presents the use of Genetic Algorithm to search for non-linear Autonomous Test Structures (ATS) in Built-In Testing approach. Such structures can include essentially STP and CSTP and their modifications. Non-linear structures are more difficult to analyze than the widely used structures such as independent Test Pattern Generator and the Test Response Compactor realized by Linear Feedback Shift Registers. To reduce time-consuming test simulation of sequential circuit, it was used an approach based on the stochastic model of pseudo-random testing. The use of stochastic model significantly affects the time effectiveness of the search for evolutionary autonomous structures. In test simulation procedure, the block of sequential circuit memory is not disconnected. This approach does not require a special selection of memory registers such as BILBOs. A series of studies to test circuits set ISCAS'89 are made. The results of the study are very promising.

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Section: Genetic Algorithm As Nlfsr Design Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Genetic algorithm as self-test path and circular self-test path design method

Chodacki

2018

Vietnam J Comput Sci

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“…In this scheme, test pattern is applied and its response is captured every test clock cycle. [6] proposed a circular self-test path (CSTP) method for test-per-clock test. [7] proposed an accumulator-based test-per-clock test generation.…”

Section: Introductionmentioning

confidence: 99%

An efficient controlled LFSR hybrid BIST scheme

Liu

2018

IEICE Electron. Express

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A new hybrid built-in self-test (BIST) test scheme is proposed. The test scheme consists of two components: the free LFSR mode (pseudorandom test) and the controlled LFSR mode (deterministic test). In order to improve the test quality of pseudo-random test sequence, a forward-backward pseudo-random test generation method is proposed. As every shifted-in bit is fully used to generate the most efficient test and the ratio of do not care bits is maximized in the remaining test pattern repository, the proposed controlled LFSR test generation method can find the targeted pattern with the minimal number of shift, efficiently embedding the deterministic test set into test-per-clock stream. Simulation results demonstrate that the proposed method considering for layout constraints shows great advantages in test data storage and test application time compared with previous methods.

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Genetic Algorithm for Self-Test Path and Circular Self-Test Path Design

Cited by 2 publications

References 11 publications

Genetic algorithm as self-test path and circular self-test path design method

Genetic algorithm as self-test path and circular self-test path design method

An efficient controlled LFSR hybrid BIST scheme

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