Built-In Self-Test for Phase-Locked Loops

Hsu, Chun-Lung; Lai, Yi‐Ting; Wang, Shuwei

doi:10.1109/tim.2005.847343

Cited by 27 publications

(28 citation statements)

References 13 publications

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“…The PD within the PLL does not drive the CP and hence it is not tested in the loop. [10] proposes a BIST mechanism with a test mode that can select between PLL output fed to the PD as against added line delay. The work presented in [11] attempts to perform parametric testing in addition to simple catastrophic failure testing proposed in many other schemes.…”

Section: Previous Workmentioning

confidence: 99%

“…The marginal failures are expected to introduce parametric failures in the PLL where design specifications may not be met due to the marginalities. A majority of work in the past such as [6], [10] is limited to catastrophic faults in the internal digital and mixed signal blocks due to lack of parametric test capability. The two fault domains are separately discussed in order to highlight confirmation with the typical coverage as well as additional parametric coverage.…”

Section: Fault Coverage Analysismentioning

confidence: 99%

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Frequency-Independent Parametric Built in Test Solution for PLLs with Low Speed Test Resources

Dasnurkar

Abraham

2012

2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop

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Phase Locked Loops (PLLs) are required to meet analog specifications such as lock time, phase error, jitter in addition to the frequency lock test in production. Parametric testing of PLLs is resource intensive and requires high precision hardware on the Automatic Test Equipment (ATE). This paper proposes a Built in Self Test (BIST) scheme to perform functional and parametric testing using low frequency ATE resources. The BIST module is independent of the PLL frequency and can be used effectively in multi-PLL System-on-a-Chip (SoC) modules. The scheme uses the Phase Detector (PD) output signature to test for lock and transient response using a digital BIST module. The BIST scheme is designed without impacting the mission mode performance by not perturbing analog nodes and the phase sensitive feedback loop. The test methodology enables parametric testing for process variation and specification compliance while using minimal external test resources. Process and operating condition independence is a critical factor to ensure compatibility with volume manufacturing and test environments.

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Section: Previous Workmentioning

confidence: 99%

Section: Fault Coverage Analysismentioning

confidence: 99%

Frequency-Independent Parametric Built in Test Solution for PLLs with Low Speed Test Resources

Dasnurkar

Abraham

2012

2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop

View full text Add to dashboard Cite

show abstract

“…The PD within the PLL does not drive the CP and therefore it is not tested in the loop. [11] proposes a BiST mechanism with a test mode that can select between PLL output fed to the PD as against added line delay. All the three schemes presented in this work use additional circuits in the feedback loop and would result in some (even if minor) phase shift as well as frequency dependence on the input signal as the at-speed signal in the feedback loop is captured and used.…”

Section: Introductionmentioning

confidence: 99%

Closed-loop Built in Self Test for PLL production testing with minimal tester resources

Dasnurkar

Abraham

2009

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop

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Phase Locked Loops (PLLs) are extensively used in modern System on a Chip (SoC) modules for generating timing, clock signal recovery and to provide a timing reference for communication interfaces. Due to their use in crucial and omnipresent applications, PLLs are the only mixed signal components on many otherwise digital blocks. The mixed signal nature makes testing of PLLs complicated as the output test requirements include non-digital parameters such as phase error, lock time, jitter along with the typical frequency locking test. Automatic Test Equipment (ATE) resources needed for these added parameters may require the use of a higher-end ATE for an otherwise digital block, driving up the production test costs. Built in Self Test (BiST) approaches for PLLs need to be carefully designed due to the load-sensitive nature of the internal analog nodes as well as sensitivity of the feedback path to any added delays by the BiST overhead. Our scheme proposes a mixedsignal closed loop complete test solution for a PLL by injecting a BiST signal at non-sensitive internal nodes and observing a low frequency(LF)/DC output in order to perform a pass/fail decision on the PLL. The goal of this scheme is to enable complete production quality at-speed testing of a PLL using minimal ATE resources.

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“…Several approaches have been proposed to screen out faulty PLLs [12]- [17]. PLLs are similar to DLLs, except they include a frequency divider in the feedback loop.…”

Section: Introductionmentioning

confidence: 99%

A BIST Circuit for DLL Fault Detection

Jia

Milor

2008

IEEE Trans. VLSI Syst.

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A built-in-self-test (BIST) circuit for the test of a delay-locked loop circuit (DLL) is proposed. This circuit is based on a simple XNOR logic gate and uncalibrated delay lines to sample the output of the XNOR gate, so very little area overhead is introduced. In addition, no external stimulus is required for this BIST circuit, besides the "start test" signal. Fault simulation results show high fault coverage of structural faults, combined with some coverage of parametric variations.Index Terms-Analog test, built-in self test (BIST), delay locked loop (DLL), fault detection, mixed signal test.

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Built-In Self-Test for Phase-Locked Loops

Cited by 27 publications

References 13 publications

Frequency-Independent Parametric Built in Test Solution for PLLs with Low Speed Test Resources

Frequency-Independent Parametric Built in Test Solution for PLLs with Low Speed Test Resources

Closed-loop Built in Self Test for PLL production testing with minimal tester resources

A BIST Circuit for DLL Fault Detection

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