Built-in dynamic current sensor for hard-to-detect faults in mixed-signal ICs

Lechuga, Y.; Mozuelos, R.; Martínez, Mar; Bracho, S.

doi:10.1109/date.2002.998271

Cited by 21 publications

(9 citation statements)

References 10 publications

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“…While such approaches are good for tolerating process variation, they do not address permanent defects and/or transient faults which are becoming inevitable due to the shrinking of feature sizes. Other approach rely on testing the analog circuit and remove bad chips from production [6]. However, no defect/fault tolerance is sought in these approaches.…”

Section: Prior Workmentioning

confidence: 98%

Scalable mean voter for fault-tolerant mixed-signal circuits

Askari

Dwivedi

Saeed

et al. 2010

2010 IEEE Aerospace Conference

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Redundancy techniques, such as N-tuple modular redundancy has been widely used to improve the reliability of digital circuits. Unfortunately nothing substantial has been done for the analog and mixed signal systems. In this paper, we propose a redundancy based fault-tolerant methodology to design a highly reliable analog and digital circuits and systems. The key contribution of our work is an innovative mean voter. This mean voter is a low power, small area, very high bandwidth and linearly scalable voting circuit. Unlike other conventional voters which works with odd N in an NMR, the mean voter works for both odd and even N for analog units and hence reduces the area and power further. For the proof of concept, we designed two fault tolerant analog circuits i.e. a low pass anti-aliasing analog filter and a 4-bit flash ADC. We also presented fault-tolerance mechanism in 4-bit binary adder and an FPGA cell for demonstrating its advantage in digital applications. Experimental results are reported to verify the concepts and measure the system's reliability when single upset transient may occur.

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Section: Prior Workmentioning

confidence: 98%

Scalable mean voter for fault-tolerant mixed-signal circuits

Askari

Dwivedi

Saeed

et al. 2010

2010 IEEE Aerospace Conference

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“…Accordingly, it can be detected. An overall schematic of the dynamic power supply current sensor, similar to the one proposed in [5], is shown in Fig. 2.…”

Section: Problem Formulationmentioning

confidence: 99%

Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator

Shi

Xiong

Chen

et al. 2011

IEEE Trans. VLSI Syst.

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Abstract-Power delivery network (PDN) is a distributed resistance-inductance-capacitance (RLC) network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips' working frequencies are much higher than this resonance frequency in general, chip runtime loading frequency is not. When a chip executes a chunk of instructions repeatedly, the induced current load may have harmonic components close to this resonance frequency, causing excessive power integrity degradation. Existing PDN design solutions are, however, mainly targeted at reducing high-frequency noise and not effective to suppress such resonance noise. In this work, we propose a novel approach to proactively suppress this type of noise. A method based on the high dimension generalized Markov process is developed to predict current load variation. Based on such prediction, a clock frequency actuator design is proposed to proactively select an optimal clock frequency to suppress the resonance. To the best of our knowledge, this is the first in-depth study on proactively reducing instruction loop induced PDN resonance noise at the runtime.

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“…Some of these faults do not produce a significant change in the quiescent current. However, they can affect the relationship of the harmonic components of the current waveform, causing a change in the slope of transient of the dynamic supply current [9].…”

Section: Built-in Current Sensormentioning

confidence: 99%

Test Based on Built-In Current Sensors for Mixed-Signal Circuits

Mozuelos

Lechuga

Martínez

et al. 2010

IFIP Advances in Information and Communication Technology

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Abstract. This paper presents a test methodology for mixed-signal circuits. The test approach uses a built-in sensor to analyze the dynamic current supply of the circuit under test. This current sensor emphasizes the highest harmonics of the dynamic current of the circuit under test when the current to voltage conversion is done. The goodness of the test method is analyzed first by means of a fault simulation and afterwards through the experimental data obtained from several benchmark circuits.

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Built-in dynamic current sensor for hard-to-detect faults in mixed-signal ICs

Cited by 21 publications

References 10 publications

Scalable mean voter for fault-tolerant mixed-signal circuits

Scalable mean voter for fault-tolerant mixed-signal circuits

Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator

Test Based on Built-In Current Sensors for Mixed-Signal Circuits

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