Building the electrical model of the pulsed photoelectric laser stimulation of a PMOS transistor in 90nm technology

Sarafianos, Alexandre; Gagliano, Olivier; Lisart, Mathieu; Serradeil, V.; Dutertre, Jean-Max; Tria, Assia

doi:10.1109/ipfa.2013.6599120

Cited by 12 publications

(5 citation statements)

References 2 publications

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“…In our work, we focused on analog electrical simulation that can provide sufficient accuracy at describing LFI while avoiding the huge computational load of physical simulation. A SPICE model for LFI was introduced in [19], [20]. This model is based on a current source that is defined by the empirical Eq.…”

Section: Development Of a Compact Model Used For Simulating Laser Bea...mentioning

confidence: 99%

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An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation

Cruz

Viera

Rigaud

et al. 2022

2022 IEEE 28th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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This work reports LFI experiments carried out on custom CMOS 65 nm digital test gates, aiming at tuning the parameters of a compact electrical model. Like in previous works, we observed a difference in behavior in the induced faults when using nanosecond and picosecond range laser pulse duration. However, our experimental results showed that the laser-sensitive areas were restricted to the PMOS transistors for ns laser pulses, contrary to what was previously stated in the literature. For ps pulse duration, these works outline the sensitivity of both the NMOS and PMOS of an SRAM cell following the theoretical model of LFI. These experiments help to calibrate the parameters of a compact electrical model, allowing the simulation of LFI attacks (using SPICE-like CAD tools). This compact model is built upon previous works, with simplifications to facilitate its use. Once tuned, simulations using the proposed compact model exhibit a good correlation with the experimental results.

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Section: Development Of a Compact Model Used For Simulating Laser Bea...mentioning

confidence: 99%

“…One aim of our approach was to demonstrate that it can be done from experiments carried out on digital gates (i.e. without the need for analog measures on dedicated test elements [20]).…”

Section: B Proposed Compact Modelmentioning

confidence: 99%

An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation

Cruz

Viera

Rigaud

et al. 2022

2022 IEEE 28th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…In the following, laser-induced SEEs are described. A laser-induced transient current is then called a 'photocurrent' [8][9][10][11][12][13][14][15][16].…”

Section: A Single Event Effects In Integrated Circuitsmentioning

confidence: 99%

“…The photocurrent generated by a pulsed-laser in an IC is generally modeled by current sources plugged in parallel to its PN junctions. The electrical models under pulsed laser stimulation (N+ on Psubstrate, P+ on Nwell and Nwell on Psubstrate) were previously introduced [10], [11], [13], [15]. We have also already published electrical models, based on these preliminary studies made from measurements and simulations, on basic structures, which create photoelectrical effects.…”

Section: Electrical Modeling Of the Pulsed Plsmentioning

confidence: 99%

SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology

Champeix

Borrel

Dutertre

et al. 2015

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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This paper presents the design of a CMOS 40 nm D Flip-Flop cell and reports the laser fault sensitivity mapping both with experiments and simulation results. Theses studies are driven by the need to propose a simulation methodology based on laser/silicon interactions with a complex integrated circuit. In the security field, it is therefore mandatory to understand the behavior of sensitive devices like D Flip-Flops to laser stimulation. In previous works, Roscian et al., Sarafianos et al., Lacruche et al. or Courbon et al. studied the relations between the layout of cells, its different laser-sensitive areas and their associated fault model using laser pulse duration in the nanosecond range. In this paper, we report similar experiments carried out using a shorter laser pulse duration (30 ps instead of 50 ns). We also propose an upgrade of the simulation model they used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology (40 nm).

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“…Photocurrent generated by a pulsed-laser on an IC, were generally modeled by current sources on PN junctions. We took the choice to improve the electrical model already introduced by Sarafianos et al in [9] and [10], which takes into accounts the laser's spot size, power, pulse duration, focus of the laser beam and the spatial parameters, location, geometry, wafer thickness.…”

Section: Photocurrent Electrical Modelmentioning

confidence: 99%

Electrical model of an inverter body-biased structure in triple-well technology under pulsed photoelectric laser stimulation

Borrel

Champeix

Kussener

et al. 2015

Microelectronics Reliability

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This study is driven by the need to optimize reliability and failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. Nowadays, Single Event Effects (SEE) evaluations due to radiation impacts are critical in fault tolerance. The prediction of a SEE on electronic device is proposed by the determination and modeling of the phenomena under pulsed laser stimulation. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on an inverter in triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals the possible activation change of the parasitic bipolar transistors. Based on these experimental measurements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation. Therefore this electrical model could be used as a tool of characterization for more complex CMOS circuits under Photoelectrical Laser Stimulation.

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Building the electrical model of the pulsed photoelectric laser stimulation of a PMOS transistor in 90nm technology

Cited by 12 publications

References 2 publications

An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation

An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation

SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology

Electrical model of an inverter body-biased structure in triple-well technology under pulsed photoelectric laser stimulation

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