Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics

Batten, Christopher; Joshi, Ajay; Orcutt, Jason S.; Khilo, Anatol; Moss, Benjamin; Holzwarth, Charles W.; Popović, Miloš A.; Li, Hanqing; Smith, Henry I.; Hoyt, Judy L.; Kärtner, F.X.; Ram, Rajeev J.; Stojanović, Vladimir; Asanović, Krste

doi:10.1109/mm.2009.60

Cited by 190 publications

(98 citation statements)

References 12 publications

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“…We call this wavelength-selective switching since the wavelength of the signal is used to determine the route that a signal will take. A network employing this type of switching has previously been proposed for use as an off-chip memoryaccess network architecture [11].…”

Section: A Methods For Routing Optical Signalsmentioning

confidence: 99%

Tools and methodologies for designing energy-efficient photonic networks-on-chip for highperformance chip multiprocessors

Chan

Hendry

Biberman

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Abstract-Photonic interconnection networks have recently been proposed as a replacement to conventional electronic networkon-chip solutions in delivering the ever increasing communication requirements of future chip multiprocessors. While photonics offers superior bandwidth density, lower latencies, and improvements in energy efficiency over electronics, the photonic network designs that can leverage these benefits cannot be easily derived by simply mimicking electronic layouts. In fact, proper implementations of photonic interconnects will require the careful consideration of a variety new physical-layer metrics and design requirements that did not exist with electronics. Here, we review some of the currently proposed designs for chip-scale photonic interconnection networks, the design methodologies required to produce viable network topologies, and a simulation environment, called PhoenixSim, that we have developed to accurately model and study those metrics and designs.

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Section: A Methods For Routing Optical Signalsmentioning

confidence: 99%

Tools and methodologies for designing energy-efficient photonic networks-on-chip for highperformance chip multiprocessors

Chan

Hendry

Biberman

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…In order to establish the communication between two chips, one should setup bidirectional optical interconnects, which usually are realized by choosing different carrier wavelengths for the forward and backward directions [167][168][169][170]. Bidirectional transmission usually has suffered from its sensitivity to backreflections, which lead to crosstalk between opposing transmitted channels and oscillation in bidirectional amplifiers.…”

Section: Bidirectional Multiplexing Technologymentioning

confidence: 99%

Silicon-based on-chip multiplexing technologies and devices for Peta-bit optical interconnects

2014

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An effective solution to enhance the capacity of an optical-interconnect link is utilizing advanced multiplexing technologies, like wavelength-division-multiplexing (WDM), polarization-division multiplexing (PDM), spatial-division multiplexing (SDM), bi-directional multiplexing, etc. On-chip (de)multiplexers are necessary as key components for realizing these multiplexing systems and they are desired to have small footprints due to the limited physical space for on-chip optical interconnects. As silicon photonics has provided a very attractive platform to build ultrasmall photonic integrated devices with CMOS-compatible processes, in this paper we focus on the discussion of silicon-based (de)multiplexers, including WDM filters, PDM devices, and SDM devices. The demand of devices to realize a hybrid multiplexing technology (combining WDM, PDM and SDM) as well as a bidirectional multiplexing technologies are also discussed to achieve Peta-bit optical interconnects.

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“…The generated packet is transmitted to the slave protocol engine and then delivers a write-ACK packet (slave protocol engine) to the master protocol engine that will inform it that a normal packet has been received (2). The slave protocol engine delivers this data to the memory controller (3). And the memory controller executes a memory access using that data on the DFI interface (4).…”

Section: International Journal Of Computer Theory and Engineering Vomentioning

confidence: 99%

“…If you need more memory capacity and more bandwidth at server-class data centers, you should attach the memory closely to the server processor [1]. In addition, the issues of more required memory bandwidth and capacity are emerging from "multi-core and many-core" that has been evolving recently [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Feasibility Test of Protocol Engines for a New Video System in Packet Communication

Kwon¹,

Choi²

2016

IJCTE

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Abstract-The layout between the processor and memory in parallel bus is very complex and difficult to place and route. The expansion of memory capacity and bandwidth is limited. A new memory system using an optical connection is proposed. We designed a serial interface using packet communication, and implemented a protocol engine to be executed on the interface. To test the feasibility of the protocol engine, we implemented a video system using an embedded processor on FPGA. The master and slave protocol engines were on the same FPGA, but used the clock differently. We conducted an experiment on the function of the proposed protocol engine between the video frame buffer and memory using a 2×10-Gbps serial link.Index Terms-Memory channel, protocol, main memory.

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Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics

Cited by 190 publications

References 12 publications

Tools and methodologies for designing energy-efficient photonic networks-on-chip for highperformance chip multiprocessors

Tools and methodologies for designing energy-efficient photonic networks-on-chip for highperformance chip multiprocessors

Silicon-based on-chip multiplexing technologies and devices for Peta-bit optical interconnects

Feasibility Test of Protocol Engines for a New Video System in Packet Communication

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