BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities

Groeseneken, G.; Franco, J.; Cho, M.; Kaczer, B.; Toledano-Luque, M.; Roussel, Ph.; Kauerauf, T.; Alian, A.; Mitard, J.; Arimura, Hiroaki; Lin, Dennis; Waldron, Niamh; Sioncke, Sonja; Witters, L.; Mertens, Hans; Ragnarsson, Lars‐Åke; Heyns, Marc; Collaert, N.; Thean, Aaron; Steegen, An

doi:10.1109/iedm.2014.7047168

Cited by 35 publications

(21 citation statements)

References 6 publications

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“…for System-on-Chip Applications Down to the 7-nm Node to the BTI degradation under sub 1-nm EOT [3] and the variability concerns [4], respectively. Meanwhile high-mobility channel materials such as III-V and Ge have been considered to substitute Si technology.…”

Section: Junction Design Strategy For Si Bulk Finfetsmentioning

confidence: 99%

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Yoon

Jeong

Baek

et al. 2015

IEEE Electron Device Lett.

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DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves RC delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based RC calculation, we suggest optimized overlap/ underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.

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Section: Junction Design Strategy For Si Bulk Finfetsmentioning

confidence: 99%

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Yoon

Jeong

Baek

et al. 2015

IEEE Electron Device Lett.

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“…The atomic origin of these defects has remained elusive. A hint might come from electrical measurements on InGaAs/Al 2 O 3 and Ge/GeO x /Al 2 O 3 interfaces which yield similar field acceleration factors, 16 but an assessment concerning the nature of the involved defects remains out of reach on this basis. More indicatively, a) Electronic mail: davide.colleoni@epfl.ch time-of-flight secondary ion mass spectroscopy studies on GaAs/Al 2 O 3 and InGaAs/Al 2 O 3 interfaces reveal the presence of In and Ga atoms in the oxide layer due to diffusion from the substrate during oxide deposition.…”

mentioning

confidence: 99%

Nature of electron trap states under inversion at In0.53Ga0.47As/Al2O3 interfaces

Colleoni

Pourtois

Pasquarello

2017

Applied Physics Letters

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In and Ga impurities substitutional to Al in the oxide layer resulting from diffusion out of the substrate are identified as candidates for electron traps under inversion at In 0.53 Ga 0.47 As/Al 2 O 3 interfaces. Through density-functional calculations, these defects are found to be thermodynamically stable in amorphous Al 2 O 3 and to be able to capture two electrons in a dangling bond upon breaking bonds with neighboring O atoms. Through a band alignment based on hybrid functional calculations, it is inferred that the corresponding defect levels lie at ∼1 eV above the conduction band minimum of In 0.53 Ga 0.47 As, in agreement with measured defect densities. These results support the technological importance of avoiding cation diffusion into the oxide layer.The microelectronic industry is investigating high mobility semiconductors for replacing silicon as substrate material. Among the III-V compounds, the In x Ga 1−x As family has gathered large interest for application in n-type devices.1 In particular, the compound In 0.53 Ga 0.47 As (here referred to as InGaAs) has suitable electronic properties for microelectronic devices and can easily be grown onto InP substrates.1,2 Amorphous Al 2 O 3 is the preferred dielectric owing to its wide bandgap, high breakdown field, and high thermal stability. 2Several passivation procedures have been considered to reduce the high density of interfacial defect states occurring at III-V/oxide interfaces (D it ).3-7 The origin of these states has been for long debated and recently assigned to As-As dimer bonds. [8][9][10][11][12][13] In addition to these interfacial states, a high density of oxide traps (D ot ) has recently been detected in the oxide layer of metal-oxide-semiconductor (MOS) devices. Capacitancevoltage (CV) measurements show a bimodal distribution for the density of defect states in the oxide, 14 with one peak at 1.5 eV above and the other at 0.5 eV below the CBM of InGaAs. Similarly, through positive bias temperature instability (PBTI) experiments, a wide distribution of defect states centered at about 1 eV above the InGaAs conduction band maximum (CBM) has been inferred.15 These states are considered to be at the origin of the degradation of the electrical properties, thereby compromising the performance of the corresponding MOS devices.14,15 Indeed, upon reaching the inversion of carrier population, the Fermi energy is pushed deep into the conduction band of InGaAs in order to achieve high carrier concentrations, and is then susceptible to defects in the upper part of the oxide band gap. The atomic origin of these defects has remained elusive. A hint might come from electrical measurements on InGaAs/Al 2 O 3 and Ge/GeO x /Al 2 O 3 interfaces which yield similar field acceleration factors, 16 but an assessment concerning the nature of the involved defects remains out of reach on this basis. More indicatively, a) Electronic mail: davide.colleoni@epfl.ch time-of-flight secondary ion mass spectroscopy studies on GaAs/Al 2 O 3 and InGaAs/Al 2 O 3 interfaces revea...

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“…For SiGe, the pre-clean before Si cap growth is more challenging [15] than in the Ge case. Using this approach, extremely good Bias Temperature Instability (BTI) has been shown [23] for Ge PMOS devices ( Figure 2). BTI is responsible for a significant shift in device parameters and as such limits the overall device lifetime, represented by the maximum overdrive voltage.…”

Section: Innovations In Gate Stackmentioning

confidence: 99%

Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling

Collaert

2016

JLPEA

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BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities

Cited by 35 publications

References 6 publications

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Nature of electron trap states under inversion at In0.53Ga0.47As/Al2O3 interfaces

Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling

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