BSM 7: RIE lag in high aspect ratio trench etching of silicon

Abstract

While etching high aspect ratio trenches into silicon with reactive ion etching (POE) using an SFJO2 chemistry it is observed that the etch rate is depending on the mask opening. This effect is known as POE lag and is caused by the depletion of etching ions and radicals or inhibiting neutrals during their trench passage. In order to decide which source is the main cause, we constructed special "horizontal trenches" where only radicals are controlling the etching. The experiment showed that radicals are not responsible for POE lag. Inhibitor depletion will result in inverse POE lag. This effect is not found during our experimentation which leaves us with ion depletion to explain POE lag. Depletion of ions is caused by ions captured by the sidewalls due to the angular distribution of incoming ions into the trench opening and the deflection of ions in the trench due to electrostatic fields• The analysis given in this paper indicates that the influencing field causes ion deflection, ion depletion, and therefore POE lag in micron-sized Si trenches for low-energetic ions• In all cases, thus independent of the feature size, the angular distribution of incoming ions is thought to have a major contribution to RIE lag at higher pressures. These phenomena will be treated theoretically and simulated using a program, written in c++ under windows, in order to give a quantitative analysis of RIE lag.

Scalable fabrication of coupled NV center - photonic crystal cavity systems by self-aligned N ion implantation

“…The mask pattern is transferred into the diamond via oxygen reactive ion (RIE) etching; hundreds to thousands of 2-d cavities can be integrated onto a single chip. The etching rate of holes in an RIE process depends heavily on the aspect ratio of the hole [33,34]. Thus, we are able to fully transfer our photonic crystal hole features (aspect ratio ∼ 2) without etching through the implantation holes (aspect ratio of ∼ 4).…”

X-ray waveguide optics

“…Although the RIE-lag is extensively documented for deep plasma etching (a,b), the same mechanisms also affect channels on length scales considered in this work [61]. For a reduced gas pressure the RIE-lag is improved [63], while the etch rate remains constant for changes of the gas pressure up to ± 20% [64]. However, the limitation to an aspect ratio of a ≈ 1.1 may even be advantageous for waveguide fabrication, leading to square shaped channels entailing a symmetrical mode structure.…”

High-uniformity centimeter-wide Si etching method for MEMS devices with large opening elements

“…[16][17][18] The first is aspect-ratio-dependent etching (ARDE). 18) ARDE is affected by the relationship between the etching rate and the ratio of etching hole depth to opening size (aspect ratio).…”