BSIM: Berkeley short-channel IGFET model for MOS transistors

Static power optimization of deep submicron CMOS circuits for dual VT technology

“…The typical VT;high and VT;low for current dual VT digital CMOS process are 0.7 and 0.25 volts respectively [12,13]. All the technology parameters for the power and delay model come from [1,2,3,5]. The signal probabilities are obtained by logic simulations with randomly generated input patterns.…”

“…For a single NMOS(PMOS) device, the Berkeley Short-Channel IGFET model (BSIM) [1] is used to estimate the leakage power dissipation. In the BSIM model, the threshold voltage is expressed as: Equation (3) gives a simple formula for the leakage current for a single NMOS device.…”

“…Thus scaling VT by the same factor as Vdd is needed so as not to adversely impact delay. However, reducing VT in small geometry MOSFETs results in a exponential increase in the stand-by current [1]. Simulation results given in [5] show that the power dissipation due to the standby current dominates the switching power at low threshold voltages.…”

Technology mapping for low leakage power and high speed with hot-carrier effect consideration

“…where µ o is the zero bias mobility, C ox is the gate oxide capacitance per unit area, kT/q is the thermal voltage, V TH0 is the zero bias threshold voltage, γ' is the linearized body effect coefficient, and η is the DIBL (Drain-induced barrier lowering) effect coefficient [1,13]. Clearly, the leakage current increases exponentially as the threshold voltage is reduced.…”

Efficient implementation selection via time budgeting: complexity analysis and leakage optimization case study

“…Therefore, we cite the relation of leakage current and delay of a MOS transistor with its threshold voltage according to their study, to maintain consistency. According to the BSIM model [1], leakage current of a MOS transistor can be approximated as follows:…”