Broadening of the variance of the number of upsets in a read-cycle by MBUs

Microelectronics Reliability

2009

Section: Techniques To Deal With Error Accumulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets

Microelectronics Reliability

2009

“…For example, in [27], it is proposed that the number of errors in an MBU can be modeled as a geometric distribution such that p(n) takes the form…”

Section: Modeling the Effects Of Mbusmentioning

confidence: 99%

“…It can be seen that the MBU case in (27) can be approximated using (28) by modifying the arrival rate in the same way as defined in (21) (29) and also assuming that…”

Section: B Scrubbingmentioning

confidence: 99%

Reliability Analysis of Memories Suffering Multiple Bit Upsets

IEEE Trans. Device Mater. Relib.

Cervantes

2007

The reliability of memory systems that are exposed to soft errors has been studied in the past with the aim of deriving the Mean Time to Failure (MTTF) and the probability of failing in a given time interval. On those studies, the soft errors were considered to arrive following a Poissonian basis and they were assumed to be single uncorrelated events (each event causes only one soft error). Recent studies suggest that Multiple Bit Upsets (MBUs) are a significant part of the error events in advanced memory technologies and that they will continue to grow in the next technology nodes. The errors in an MBU are normally caused by the same physical event and therefore affect memory cells that are close together. This poses a major problem to memories that are protected with per-word Single Error Correction codes, as an MBU is likely to affect two or more bits in the same word, causing an uncorrectable error. To avoid that problem, interleaving is used to ensure that cells that are physically close together belong to different logical words, so that the errors in an MBU are distributed over a number of words each suffering only one error. Although some works have been done that characterize memories under radiation tests, no mathematical model of the effect of MBUs on the reliability of a memory has been proposed in the literature, to the best of the authors' knowledge. Therefore, in this paper, the reliability of memories suffering MBUs is analyzed in detail. The fundamental result from that analysis is that the MTTF of a memory exposed to MBUs can be approximated using the existing results for single event upsets by adjusting the error arrival rate.

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“…In this way, the accumulation of errors over time is avoided, thus minimizing the probability of failure [Saleh et al 1990;Goodman et al 1991;Yang 1995]. More recent research focuses on the effects of Multiple Bit Upsets (MBUs) [Radaelli et al 2005;Tipton et al 2006;Maiz et al 2003;Chugg et al 2004] on memory reliability [Reviriego et al 2007]. MBUs affect bits stored on physically adjacent memory cells.…”

Section: Introductionmentioning

confidence: 99%

Reliability analysis of memories protected with BICS and a per-word parity bit

ACM Trans. Des. Autom. Electron. Syst.

Bleakley

2010