Broad band software-defined radio receivers based on superconductive devices

Recent progress in single flux quantum (SFQ) device technologies in Japan is described, mainly focusing on those developed in the NEDO "Superconductors Network Device Project" which includes developments of both LTS and HTS devices. The advanced Nb process which consists of a planarized structure with nine Nb layers and 10 kA cm 2 Josephson junctions (JJs) has been developed. This enables fabrication of chips including 100,000 JJs and operating frequency up to 80 GHz. We have also developed the CAD tool by which one can generate SFQ circuit layouts including about 400,000 JJs from logic descriptions. For demonstration of a small-scale switch system, a 4 4 switch chip, a 117 Gbps multichip-module (MCM) technology, and a packaging technology with 32-ch 10 Gbps I/Os to an MCM have been developed. By using the multilayer process with three HTS epitaxial layers and interfaceengineered ramp-edge JJs, we demonstrated operation of SFQ circuits with up to 200 JJs. A variety of elementary SFQ circuits such as a T-FF and a 1:2 switch required for an A/D converter front-end circuit have been designed based on a new layout method, and their operation at 30-50 K has been confirmed. A prototype sampler system is being developed for demonstration of bandwidth over 100 GHz for optical input signals.

Section: Sampler Systems and A/d Convertermentioning

confidence: 99%

Recent Progress in SFQ Device Technologies in Japan

Tanabe

Hidaka

2007

“…Generally, the maximum rms uncertainty, or jitter, of the sampling clock allowed for -bit A/D converters is expressed by (1) where is the signal bandwidth. In order to achieve 14-bit resolution for the signal bandwidth of 10 MHz, for example, the rms jitter should be less than 2 ps.…”

Section: A Concept Of Frequency Multiply Circuitmentioning

confidence: 99%

“…T HE superconducting sigma-delta A/D converter with high resolution and rather high bandwidth has attracted much attention because of its potential application to next-generation wireless communication [1], [2]. With the aim of realizing resolution high enough for such application, various types of high-order modulators have been investigated [3].…”

Section: Introductionmentioning

confidence: 99%

Frequency Multiply Circuit for Superconducting A/D Converter

Yoshida¹,

Hirano²,

Suzuki³

et al. 2005

A new frequency multiply circuit generating a 20 GHz sampling clock from an external 5 GHz signal for a lowpass sigmadelta modulator was proposed and designed. The multiply circuit was composed of a ladder circuit, a modified Josephson transmission line (JTL) and T-flip flop (T-FF). We confirmed by numerical simulation that the period jitter of SFQ pulse trains generated by the ladder circuit could be reduced to a value small enough to realize 14-bit resolution for 10 MHz bandwidth by utilizing the repulsion effect between SFQ pulses in the modified JTL. The multiply circuit was fabricated by a 2.5 kA cm 2 Nb process, and its correct operation was confirmed.Index Terms-Analog-to-digital converter, frequency multiply circuit, Josephson device, rapid single flux quantum circuit, sigmadelta modulator.

“…Therefore, SFQ-ADCs can achieve broad bandwidth and high sensitivity. These characteristics are suitable for the front-end of the software defined radio receivers [2], [3] and sensors to pick up weak signals [4].…”

Section: Introductionmentioning

confidence: 99%

Demonstration of the Multi-Bit Sigma-Delta A/D Converter With the Decimation Filter

Sekiya

Okada

Yoshinori

et al. 2005

Self Cite

We have proposed a multi-bit sigma-delta analog-todigital converter (ADC) in which a modulator is composed of a single quantizer and multiple samplers based on the single-flux-quantum (SFQ) circuits. The quantizer converts analog signals to pulse-density-modulated signals, and the samplers sample the modulated SFQ pulses in every sampling clock. Use of multiple samplers based on delayed-flip-flops (DFFs) increases sampling frequencies virtually, resulting in a multi-bit sigma-delta modulator. We also designed a decimation filter by using the well-established Verilog tools for the SFQ circuits and the Matlab simulator. We prepared an ADC including 4 samplers and a second-order decimation filter with the decimation rate of 1:256 based on the Nb junction technology. We confirmed correct operation of this ADC at 56 GHz clock signals generated by an internal ring oscillator. We experimentally obtained the signal-to-noise ratio of 25 dB and spurious-free dynamic range of 37 dB at the bandwidth of 10 MHz from the upper 7 bits of the outputs of the decimation filter.