Bringing NoCs to 65 nm

Pullini, Antonio; Angiolini, Federico; Murali, Srinivasan; Atienza, David; Micheli, Giovanni De; Benini, Luca

doi:10.1109/mm.2007.4378785

Cited by 57 publications

(49 citation statements)

References 16 publications

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“…Pullini et al provide the basis for our interconnect latency modeling [28]. For the in-order cores, instructions-per-cycle (IPC) is assumed to be one except for memory references, which are modeled faithfully through the memory hierarchy (although we do not model memory controller effects).…”

Section: A Simulationmentioning

confidence: 99%

Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling

Meng

Skadron

2009

2009 IEEE International Conference on Computer Design

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Abstract-Without high-bandwidth broadcast, large numbers of cores require a scalable point-to-point interconnect and a directory protocol. In such cases, a shared, inclusive last level cache (LLC) can improve data sharing and avoid threeway communication for shared reads. However, if inclusion encompasses thread-private data, two problems arise with the shared LLC. First, current memory allocators align stack bases on page boundaries, which emerges as a source of severe conflict misses for large numbers of threads on data-parallel applications. Second, correctness does not require the private data to reside in the shared directory or the LLC. This paper advocates stack-base randomization that eliminates the major source of conflict misses for large numbers of threads. However, when capacity becomes a limitation for the directory or last-level cache, this is not sufficient. We then propose non-inclusive, semi-coherent cache organization (NISC) that removes the requirement for inclusion of private data and reduces capacity misses. Our data-parallel benchmarks show that these limitations prevent scaling beyond 8 cores, while our techniques allow scaling to at least 32 cores for most benchmarks. At 8 cores, stack randomization provides a mean speedup of 1.2X, but stack randomization with 32 cores gives a speedup of 2.7X over the best baseline configuration. Comparing to conventional performance with a 2 MB LLC, our technique achieves similar performance with a 256 KB LLC, suggesting LLCs may be typically overprovisioned. When very limited LLC resources are available, NISC can further improve system performance by 1.8X.

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Section: A Simulationmentioning

confidence: 99%

Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling

Meng

Skadron

2009

2009 IEEE International Conference on Computer Design

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“…While techniques such as link pipelining have been proposed to overcome link latency [64,70], the cycle-level synchronicity severely constrains the clock distribution [78] and negatively affects the scalability [12]. A range of asynchronous networks [3,10,66] completely remove the need for a clock, and aim to leverage the characteristics of asynchronous circuits to reduce power and electromagnetic emissions.…”

Section: Physical Scalabilitymentioning

confidence: 99%

“…This in turn causes layout issues (e.g. timing and packing) and negatively affects performance [64]. Although the problem can be mitigated by using a partial crossbar [54], the key to architectural scalability is a distributed multi-hop interconnect.…”

Section: Architectural Scalabilitymentioning

confidence: 99%

“…[3,10,59,64,66] and those where arbitration only takes place only at the edges (NIs) of the network, as done in Nostrum [50], aSoC [45], AEthereal [26], and TTNoC [60]. The works in [3,10,59,64,66] use virtual channels to provide connection-based services. As a consequence, the router area grows quadratically with the number of connections passing through the router.…”

Section: Architectural Scalabilitymentioning

confidence: 99%

“…NoCs address the physical scalability by splitting the interconnect into multiple segments with relaxed timing requirements [16,64] and offer architectural scalability through a structured and modular architecture [6]. It is thus possible to implement a network that scales with the number of IPs in the design [43,72].…”

Section: Introductionmentioning

confidence: 99%

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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

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A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level.Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e. the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked. The onus is on the interconnect design flow that translates user requirements to an interconnect instance. While mature tooling exists for many of the IPs, interconnect design flows are an active research area, with few concrete examples, and few large-scale case studies.As the main contribution of this work, we demonstrate a complete operational interconnect design flow for multiple real-time applications, and quantitatively evaluate the functional scalability on two large-scale industrial case studies. We illustrate the steps of the flow, going from requirement specification all the way to simulation of synthesised netlists in a 90 nm and 65 nm low-power standard-cell technology. We show that the interconnect and design flow offer scalability, on the physical, architectural as well as the functional level.

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