Bridging the genotype-phenotype mapping for digital FPGAs

Haddow, Pauline C.; Tufte, Gunnar

doi:10.1109/eh.2001.937952

Cited by 54 publications

(28 citation statements)

References 14 publications

(15 reference statements)

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“…A disadvantage of the approach is the increased resource usage overhead associated with having to implement all possible connections and functionality. This method has been termed virtual reconfigurable circuit (VRC) [30] or virtual FPGA [8] in earlier work.…”

Section: Ehw Variantsmentioning

confidence: 99%

A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device

Glette

Tørresen

2005

Evolvable Systems: From Biology to Hardware

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Section: Ehw Variantsmentioning

confidence: 99%

A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device

Glette

Tørresen

2005

Evolvable Systems: From Biology to Hardware

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“…Figure 1 illustrates the Virtual Sblock FPGA: the grid of Sblocks; local connections between neighbouring Sblocks and the internal logic of an Sblock. The Virtual Sblock FPGA [8] contains blocks -Sblocks -laid out as a symmetric grid where neighbouring blocks are connected. Each Sblock neighbours onto Sblocks on its four sides (north N, east E, south S and west W).…”

Section: Virtual Sblock Fpgamentioning

confidence: 99%

“…A detailed description of Sblocks and the Virtual Sblock FPGA is presented in [8]. Evolution and development friendly features of the platform may be found in [11].…”

Section: Virtual Sblock Fpgamentioning

confidence: 99%

Biologically-Inspired: A Rule-Based Self-Reconfiguration of a Virtex Chip

Tufte

Haddow

2004

Computational Science - ICCS 2004

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Abstract. To be able to evolve digital circuits with complex structure and/or complex functionality we propose an artificial development process as the genotype-phenotype mapping. To realistically evolve such circuits a hardware implementation of the development process together with high-speed reconfiguration logic for phenotype implementation is presented. The hardware implementation of the development process is a programmable reconfiguration processor. The high-speed reconfiguration logic for evaluation of the phenotype is capable of exploiting the advantage of massive parallel processing due to the cellular automata like structure.

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“…The field of Evolvable HardWare (EHW), which encompasses the design of electronic circuits using EAs, has not yet achieved the design of complex circuits. Hence, enhancing the power of EAs in order to achieve more complex circuit designs has been a subject to extensive research in EHW [1]- [6]. The ability to scale to larger and higher complexity circuits in a reasonable amount of time is termed scalability.…”

Section: Introductionmentioning

confidence: 99%

A scalable solution to n-bit parity via artificial development

Kuyucu

Trefzer

Miller

et al. 2009

2009 Ph.D. Research in Microelectronics and Electronics

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Abstract-The design of electronic circuits with model-free heuristics like evolutionary algorithms is an attractive concept and field of research. Although successful to a point, evolution of circuits that are bigger than a 3-bit multiplier is hindered by the scalability problem. Modelling the biological development as an artificial genotype-phenotype mapping mechanism has been shown to improve scalability on some simple circuit problems and pattern formations. As a candidate solution to the scalability issue, an artificial developmental system is presented.The presented artificial developmental system is shown to develop a scalable parity circuit, which could be infinitely developed to build a growing parity circuit, hence, represents a general, scalable solution to n-bit parity.The result obtained further supports the artificial developmental system as a good candidate solution to the scalability problem in evolvable hardware.

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Bridging the genotype-phenotype mapping for digital FPGAs

Abstract: Abstract

Cited by 54 publications

References 14 publications

A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device

A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device

Biologically-Inspired: A Rule-Based Self-Reconfiguration of a Virtex Chip

A scalable solution to n-bit parity via artificial development

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