A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device

Glette, Kyrre; Tørresen, Jim

doi:10.1007/11549703_7

Cited by 35 publications

(26 citation statements)

References 40 publications

(38 reference statements)

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“…op of the device and [9], implies urations of the ce, selecting the rs driven by the guration process n be done in just reconfigurable by the inclusion y single function ng, reducing the re, the use of runan alternative to pegui proposes in sists in changing ning. The second able modules of a g structure.…”

Section: Evolvable Hardwarementioning

confidence: 99%

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

Otero

Salvador

Mora

et al. 2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Section: Evolvable Hardwarementioning

confidence: 99%

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

Otero

Salvador

Mora

et al. 2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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“…While most related work in CGP aims at evolutionary circuit design where hardware mapping is required only once after an appropriate circuit has been evolved, there are two cases for which an efficient FPGA mapping is of utmost importance. The first is the use of FPGAs as accelerators to speed up the fitness evaluation, e.g., in [6]. The second and presumably more challenging one is on-chip evolution [7,12].…”

Section: Fpga Mappingmentioning

confidence: 99%

“…However, there is a lack of open FPGA bitstream architectures which makes the creation of custom routing and bitstream generation tools a research challenge on its own. For that reason, several researchers resorted to virtual FPGAs and implemented routing by controlling multiplexers that select between different datapaths [21,6].…”

Section: Fpga Mappingmentioning

confidence: 99%

Advanced techniques for the creation and propagation of modules in cartesian genetic programming

Kaufmann

Platzner

2008

Proceedings of the 10th Annual Conference on Genetic and Evolutionary Computation

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The choice of an appropriate hardware representation model is key to successful evolution of digital circuits. One of the most popular models is cartesian genetic programming, which encodes an array of logic gates into a chromosome. While several smaller circuits have been successfully evolved on this model, it lacks scalability. A recent approach towards scalable hardware evolution is based on the automated creation of modules from primitive gates.In this paper, we present two novel approaches for module creation, an age-based and a cone-based technique. Further, we detail a cone-based crossover operator for use with cartesian genetic programming. We evaluate the different techniques and compare them with related work. The results show that age-based module creation is highly effective, while cone-based approaches are only beneficial for regularly structured, multiple output functions such as multipliers.

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“…The coding was done using VHDL and simulated to test its correctness using Xilinx ISE 11.1. Some reported studies have used a hardware/software hybrid design, where some parts of the GA, especially the fitness function, are implemented in hardware [9,10] and the rest of the GA is implemented in software. However, in this study, all components of the GA are implemented in hardware.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of a genetic algorithm IP core on an FPGA for path planning of mobile robots

Tuncer¹,

Yildirim²

2016

Turk J Elec Eng & Comp Sci

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This paper presents a hardware realization of a genetic algorithm (GA) for the path planning problem of mobile robots on a field programmable gate array (FPGA). A customized GA intellectual property (IP) core was designed and implemented on an FPGA. A Xilinx xupv5-lx110t FPGA device was used as the hardware platform. The proposed GA IP core was applied to a Pioneer 3-DX mobile robot to confirm its path planning performance. For localization tasks, a camera mounted on the ceiling of the laboratory was utilized to receive images and allow the robot to determine its own location and the obstacles in the environment. In this way, procedures of path planning were tested in a real laboratory environment. An impressive time speedup was achieved when compared with its software implementation.Experimental results illustrate the effectiveness of the GA IP core hardware.

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A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device

Cited by 35 publications

References 40 publications

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

Advanced techniques for the creation and propagation of modules in cartesian genetic programming

Design and implementation of a genetic algorithm IP core on an FPGA for path planning of mobile robots

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