Bridging defects resistance measurements in a CMOS process

Rodríguez-Montañés, R.; Bruis, E.M.J.G.; Figueras, J.

doi:10.1109/test.1992.527915

Cited by 165 publications

(70 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Researchers have shown that 98.3% of resistive shorts are below 5KΩ [13]. Consequently, the supply voltage for VLV testing should be in the range of 2V t and 2.5V t , where V t is the smaller between V tn and |V tp |.…”

Section: Metal Shortsmentioning

confidence: 99%

Quantitative analysis of very-low-voltage testing

Chang

McCluskey

Proceedings of 14th VLSI Test Symposium

View full text Add to dashboard Cite

show abstract

Section: Metal Shortsmentioning

confidence: 99%

Quantitative analysis of very-low-voltage testing

Chang

McCluskey

Proceedings of 14th VLSI Test Symposium

View full text Add to dashboard Cite

show abstract

“…We consider all possible BFs, with realistic values of connecting resistance (RBF) in the [0..6k] range [17]. Their activating conditions, as well as their produced effects during both the DA and TX operating modes are summarized in Table 1.…”

Section: Bridging Faults (Bfs) Affecting the Ac/dcmentioning

confidence: 99%

“…We have considered a set of faults F possibly affecting our monitor composed by node stuck-ats (SAs), transistor stuckopens (SOPs), transistor stuck-ons (SONs) and resistive bridgings (BFs), with values of connecting resistance R in the range [0..6k] [17]. We have analyzed their effects by means of logical and electrical simulations.…”

Section: Self-checking Abilitymentioning

confidence: 99%

Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection

Omaña

Rossi

Giaffreda

et al. 2013

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).

show abstract

“…To model a short between two wires, a new resistor connected to both of them is inserted. We consider 10 different short circuit resistances between 10 to 15000 Ω, which covers the range of hard and resistive shorts [37]. Altogether, there are 13 short locations and 10 different short circuit resistances between 10 to 15000 Ω.…”

Section: Fault Injectionmentioning

confidence: 99%

Variation-aware fault modeling

Hopsch

Becker

Hellebrand

et al. 2011

Sci. China Inf. Sci.

View full text Add to dashboard Cite

To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by Science China Press and Springer-Verlag Berlin Heidelberg. 1 Fraunhofer IIS/EAS, Dresden D-010169,G e r m a n y 2 University of Freiburg, Freiburg D-79110,G e r m a n y 3 University of Paderborn, Paderborn D-33098,G e r m a n y 4 University of Passau, Passau D-94023,G e r m a n y 5 University of Stuttgart, Stuttgart D-70569,G e r m a n y Received March 21, 2011; accepted June 21, 2011Abstract To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level i...

show abstract

Bridging defects resistance measurements in a CMOS process

Cited by 165 publications

References 7 publications

Quantitative analysis of very-low-voltage testing

Quantitative analysis of very-low-voltage testing

Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection

Variation-aware fault modeling

Contact Info

Product

Resources

About