Breaking the Design and Security Trade-off of Look-up-table–based Obfuscation

Abstract

Logic locking and Integrated Circuit (IC) camouflaging are the most prevalent protection schemes that can thwart most hardware security threats. However, the state-of-the-art attacks, including Boolean Satisfiability (SAT) and approximation-based attacks, question the efficacy of the existing defense schemes. Recent obfuscation schemes have employed reconfigurable logic to secure designs against various hardware security threats. However, they have focused on specific design elements such as SAT hardness. Despite meeting the focused criterion such as security, obfuscation incurs additional overheads, which are not evaluated in the present works. This work provides an extensive analysis of Look-Up-Table (LUT)-based obfuscation by exploring several factors such as LUT technology, size, number of LUTs, and replacement strategy as they have a substantial influence on Power-Performance-Area (PPA) and Security (PPA/S) of the design. We show that using large LUT makes LUT-based obfuscation resilient to hardware security threats. However, it also results in enormous design overheads beyond practical limits. To make the reconfigurable logic obfuscation efficient in terms of design overheads, this work proposes a novel LUT architecture where the security provided by the proposed primitive is superior to that of the traditional LUT-based obfuscation. Moreover, we leverage the security-driven design flow, which uses off-the-shelf industrial EDA tools to mitigate the design overheads further while being non-disruptive to the current industrial physical design flow. We empirically evaluate the security of the LUTs against state-of-the-art obfuscation techniques in terms of design overheads and SAT-attack resiliency. Our findings show that the proposed primitive significantly reduces both area and power by a factor of 8 × and 2 ×, respectively, without compromising security.

A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs

“…Countermeasures to secure an IC also apply to a malicious end-user that can be interested in reverse engineering a design. Noteworthy examples of countermeasures are Logic Locking [6]- [10], IC Camouflaging [11]- [13], Split Manufacturing [14], [15], and FPGA-like obfuscation approaches [16]- [24]. The latter style of obfuscation attempts to exploit an FPGA (or FPGA-like) fabric, where the functionality of the circuit is hidden by the configuration and the bitstream serves as a key to unlock the design.…”

Design of secure and robust cognitive system for malware detection

“…The hardware security discipline in recent years experienced a plethora of threats like the Malware attacks [1][2][3][4][5][6][7], Side-Channel Attacks [8][9][10][11], Hardware Trojan attacks [12], reverse engineering threats [13][14][15][16][17][18][19][20][21][22][23][24][25][26] and so on. I focus on the malware detection technique here along with some state-of-the-art works.…”