Breakdown in the metal/high-k gate stack: Identifying the &amp;#x201C;weak link&amp;#x201D; in the multilayer dielectric

Bersuker, G.; Heh, D.; Young, C.D.; Park, H.; Khanal, Prabhat; Larcher, Luca; Padovani, Andrea; Lenahan, Patrick M.; Ryan, Jason T.; Lee, Byoung Hun; Tseng, Hsing Huang; Jammy, R.

doi:10.1109/iedm.2008.4796816

Cited by 64 publications

(63 citation statements)

References 12 publications

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“…The dotted area shows a location with higher electric field across the IL beneath the GBs associated with the low resistance path in the HfO 2 layer. It should be noted that the IL beneath the GBs become oxygen deficient layer [16,17] and its dielectric constant might be higher than 3.9. Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer

Shubhakar

Raghavan

Kushvaha

et al. 2014

Microelectronics Reliability

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Section: Simulation Resultsmentioning

confidence: 99%

Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer

Shubhakar

Raghavan

Kushvaha

et al. 2014

Microelectronics Reliability

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“…High-κ layers are prone to the formation of both native and stress induced defects. Hence, they wear out relatively faster than the IL layer and the ultra-thin IL layer determines the final catastrophic breakdown [27].…”

Section: Time Dependent Dielectric Breakdown (Tddb)mentioning

confidence: 99%

“…The actual reason behind the SILC is a controversial issue. While some groups attribute the SILC phenomenon to the defect generation in the HK layers [30,34,35], others explain SILC by defect generation only in the IL layer [27,36]. J. Yang, et al [13] argued that SILC is caused by defects in both HK and IL layers but mostly dominated by the defects in the IL layer since they have much lower relaxation energy.…”

Section: Stress-induced Leakage Current (Silc)mentioning

confidence: 99%

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

Hassan

Roy

2017

Microelectronics Reliability

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Abstract-Bias Temperature Instability (BTI) is a majorreliability concern in CMOS technology, especially with High dielectric constant (High-κ/HK) metal gate (MG) transistors. In addition, the time independent process induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in the BTI degradation. Since time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time zero variability on all these effects simultaneously.To that effect, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000 nm 2 ) in 30nm technology, we observe significant effect of Random Dopant Fluctuation (RDF) on BTI induced variability (σ ΔVth ). In addition, the circuit analysis reveals similar trend on the performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on V th degradation cannot be disregarded in scaled technology and needs to be considered for variation tolerant circuit design.

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“…3,4 The high-k/metal gate (HKMG) stacks shows, e.g., progressive stress induced leakage current (SILC) behavior under operation. Two different models for high-k SILC are discussed in the literature: the degradation of the interfacial SiO 2 layer (IL) 5,6 and defect related processes like, e.g., trap-assisted tunneling (TAT) or charge trapping within the high-k layer. [7][8][9] In bulk HfO 2 , oxygen related defects are the predominant intrinsic defects.…”

mentioning

confidence: 99%

Charge transition levels of oxygen, lanthanum, and fluorine related defect structures in bulk hafnium dioxide (HfO2): An ab initio investigation

Leitsmann¹,

Lazarevic²,

Nadimi

et al. 2015

Journal of Applied Physics

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Intrinsic defect structures and impurity atoms are one of the main sources of leakage current in metal-oxide-semiconductor devices. Using state of the art density functional theory, we have investigated oxygen, lanthanum, and fluorine related defect structures and possible combinations of them. In particular, we have calculated their charge transition levels in bulk m-HfO2. For this purpose, we have developed a new scaling scheme to account for the band gap underestimation within the density functional theory. The obtained results are able to explain the recent experimental observation of a reduction of the trap density near the silicon valence band edge after NF3 treatment and the associated reduction of the device degradation.

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Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric

Cited by 64 publications

References 12 publications

Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer

Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

Charge transition levels of oxygen, lanthanum, and fluorine related defect structures in bulk hafnium dioxide (HfO2): An ab initio investigation

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