Branch-Aware Loop Mapping on CGRAs

Hamzeh, Mahdi; Shrivastava, Aviral; Vrudhula, Sarma

doi:10.1145/2593069.2593100

Cited by 15 publications

(3 citation statements)

References 23 publications

(22 reference statements)

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“…In this case, the modulo scheduling was able to exploit this improvement and continue achieving quasi-optimal ILP. Future works include evaluating the acceleration considering larger application blocks and conditional branches [15], as well as on-the-fly generation of the CGRA using customized functional units.…”

Section: Discussionmentioning

confidence: 99%

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A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Ferreira

Denver

Pereira

et al. 2015

J Sign Process Syst

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In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to optimize loops by using software pipelining approaches. They are proven to be effective in reducing the total execution time of multimedia and signal processing applications. However, the run-time reconfigurability of CGRAs is hampered overheads introduced by the needed translation and mapping steps. In this work, we present a novel run-time translation technique for the modulo scheduling approach that can convert binary code onthe-fly to run on a CGRA. We propose a greedy approach, since the modulo scheduling for CGRA is an NP-complete problem. In addition to read-after-write dependencies, the dynamic modulo scheduling faces new challenges, such as register insertion to solve recurrence dependences and to balance the pipelining paths. Our results demonstrate that the greedy run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for a 16-issue VLIW processor. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated. In this analysis it is demonstrated R. Ferreira ( ) · W. Denver that when changing from one memory access per cycle to two memory accesses per cycle, the modulo scheduling algorithm is able to exploit this increase in memory bandwidth and enhance performance accordingly. Additionally, to measure area and performance, the proposed CGRA was prototyped on an FPGA. The area comparisons show that a crossbar CGRA (with 16 processing elements and including an 4-issue VLIW host processor) is only 1.11 × bigger than a standalone 8-issue VLIW softcore processor.

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Section: Discussionmentioning

confidence: 99%

“…Assuming two operand instructions (algorithm lines [13][14][15][16][17][18][19][20][21][22]. There are three cases: (1) two inputs; (2) one input and one RAW; and (3) two RAWs.…”

Section: Bt Ms Algorithmmentioning

confidence: 99%

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Ferreira

Denver

Pereira

et al. 2015

J Sign Process Syst

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“…However, there is still no single technique which is optimal across all types of control flow, so composite methods are the only choice [3,7].…”

Section: Introductionmentioning

confidence: 99%

Acceleration of control flows on reconfigurable architecture with a composite method

Wang

Liu

Zhu

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Control-intensive kernels are becoming the bottleneck that limits the performance of Coarse-Grained Reconfigurable Architecture. Some methods, such as predicated execution, speculative execution, and dual-issue-single-execution, have been proposed to alleviate this problem. But they cannot be always efficient for various control flows. This paper proposes a new architecture, which combines the techniques of triggered instruction and parallel condition, in order to solve the problem completely. The architecture utilizes the basic framework of the triggered instruction to avoid over-serialized execution and branch instruction. Meanwhile, it takes the mechanism of the parallel condition to explore the parallelism between predicate and compute instructions without reconciliation operations. The mechanism of executing multiple instructions that have internal control dependence in parallel is discussed as well. The experiment result shows that the proposed architecture can achieve 20.9% to 140.0% higher performance than that of triggered instruction architecture in terms of cycle count.

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4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs

Karunaratne

Wijerathne

Mitra

et al. 2019

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Branch-Aware Loop Mapping on CGRAs

Cited by 15 publications

References 23 publications

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Acceleration of control flows on reconfigurable architecture with a composite method

4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs

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