Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems

Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms

“…However, we believe it is likely that the hypothesis holds on other platforms as well, since several previous studies have highlighted that worst-case delays are generated when hardware request queues saturate [63,12], and maximizing concurrent activity of all cores increases the probability of such occurrence. Furthermore, in case the hypothesis does not hold, but a precise model of main memory is available, we argue that a more complex analysis, along the lines of [35,73], could be used to bound the maximum delay suffered by the kernel. Third, our approach requires modifications to the code of each GPU kernel.…”

“…Contention in shared memory among multiple processing elements can lead to a very high increase in memory access latency [44,63,35]. The Predictable Execution Model (PREM), first proposed in [53], introduces a method for prevent contention in the shared memory of multi-core platforms.…”

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

“…The scope of this survey is restricted to timing verification techniques for multi-core and manycore platforms that specifically consider the impact of shared hardware resources. The following areas of related research are outside of the scope of this survey: (i) works that introduce isolation mechanisms for multi-core systems, but rely on existing analysis for timing verification (examples include the work on the MERASA [94] and T-CREST projects [111], as well as work on shared cache management techniques (surveyed in [46]) and cache coherence [47,56]; (ii) works that introduce mechanisms and analyses of the worst-case latencies for a particular component, for example predictable DDR-DRAM memory controllers 4 (comparative studies in [49,57]), but rely on these latencies being incorporated into existing analyses for timing verification; (iii) scheduling and schedulability analyses for multiprocessor systems that consider only a simple abstract model of task execution times (surveyed in [38]); (iv) multiprocessor software resource sharing protocols; (v) timing verification techniques for many-core systems with a Network-on-Chip (NoC) (surveyed in [59,70]) which consider only the scheduling of the NoC, or consider that tasks on each core execute out of local memory with the only interaction with packet flows being through a consideration of release jitter; (vi) measurement-based and measurement-based probabilistic timing analysis methods; (vii) research that focuses on timing verification of single-core systems. Further, the survey does not cover specific research into multi-cores with GPGPUs or re-configurable hardware.…”

On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?

“…These efforts follow two major directions. The first direction is to analyze existing memory controllers used in conventional high-performance systems to upper bound the latency suffered by any request upon accessing DDRx main memory [3], [4], [22]. Following a similar direction, [23] targets to bound DRAM interference in conventional platforms by enforcing bank partitioning at the operating system level.…”