Bounded-skew clock and Steiner routing

Abstract

We study the minimum-cost bounded-skew routing tree problem under the pathlength (linear) and Elmore delay models. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. Our bounded-skew routing algorithm, called the BST/DME algorithm, extends the DME algorithm for exact zero-skew trees via the concept of a merging region. For a prescribed topology, BST/DME constructs a bounded-skew tree (BST) in two phases: (i) a bottom-up phase to construct a binary tree of merging regions which represent the loci of possible embedding points of the internal nodes, and (ii) a top-down phase to determine the exact locations of the internal nodes. We present two approaches to construct the merging regions: (i) the Boundary Merging and Embedding (BME) method which utilizes merging points that are restricted to the boundaries of merging regions, and (ii) the Interior Merging and Embedding (IME) algorithm which employs a sampling strategy and a dynamic programming-based selection technique to consider merging points that are interior to, as well as on the boundary of, the merging regions. When the topology is not prescribed, we propose a new Greedy-BST/DME algorithm which combines the merging region computation with topology generation. The Greedy-BST/DME algorithm very closely matches the best known heuristics for the zero-skew case and for the unbounded-skew case (i.e., the Steiner minimal tree problem). Experimental results show that our BST algorithms can produce a set of routing solutions with smooth skew and wirelength tradeoffs.

Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations

“…Two more industry cases JPEG1 and JPEG3 are tested in this paper. The initial zero-skew tree is constructed by the GDME [4] method under the Elmore delay model with no temperature variation. The interconnect has unit resistance r 0 = 0.1Ω/mum, unit capacitance c0 = 2.0 × 10 −16 F/μm, and temperature sensitivity β = 0.0068, The above interconnect parameters are the same as those in TACO [6].…”

“…Given a set of sinks (flip-flops), clock synthesis finds an abstract topology, embedding and minimizes mismatch of arrival times (i.e., skew) between sinks. Wire length minimizations under zero or bounded skew constraint were presented in [1], [2], [4]. However, process, supply voltage, and temperature variation induced skews were not considered.…”

“…However, process, supply voltage, and temperature variation induced skews were not considered. The exponential advance of very large scale integration (VLSI) technology has resulted in a high and non-uniform power dissipation over chips [4], which leads to a temperature gradient, i.e., spatial temperature variation over a chip that can cause non-negligible delay differences in both interconnects and devices. As clock signals are globally routed over chip, the temperature gradient can bring significant skew variations [5].…”

The associative-skew clock routing problem

“…Our experiments compare the performance (based on total tree wirelength) of these heuristics on synthetic data. 6 We additionally assess implementations of Greedy-DME (GDME); the GDME1 implementation runs GDME with the sink offsets used by H2, while the GDME2 implementation runs GDME with all sink offsets = 0. Runtimes are reported for H2 (Time1; H3 runtimes are essentially the same) and for GDME1 (Time2; GDME2 runtimes are essentially the same), measured in CPU seconds on a 300MHz Sun Ultra-10 workstation with 512MB RAM.…”

“…Hence, the bounded-skew tree (BST) problem was addressed in [14,7,16,6]. The BST problem provides a continuous tradeoff between two classic routing problems -the zero-skew tree (ZST) problem for skew bound B = 0, and the rectilinear Steiner minimum tree (RSMT) problem for B = ∞.…”