“…The n+ regions were formed by thermal diffusion from the deposited PSG (phosphosilicate glass) films, and the p+ regions were formed by boron ion implantation. The PD arrays are formed by the Bosch process using deep reactive ion etching (Deep RIE) [32][33] [34]. Its trench width is 20 µm at the top of the chip and 15 µm at its bottom, and its silicon substrate thickness is 540 µm.…”
In this paper, we report a method of increasing the sensitivity of a silicon near-infrared sensor. The sensor is realized by forming multiple trench-type photodiodes in a silicon chip. The trench photodiodes can be formed using conventional semiconductor fabrication equipment. The device structure allows the depletion layer to be spread over the entire sensor chip even at a bias voltage of 10 V or less. The sensor chip can thereby extend the collection area of photoelectrons to the maximum. At a chip thickness of 540 µm, the conversion efficiency for near-infrared wavelengths between 940 and 1020 nm is more than 80% at room temperature. In addition, the electrical characteristics and response performance of the fabricated 2.4 mm × 2.4 mm test chips are reported. Since the proposed method can achieve a high conversion efficiency at low voltage without cooling in silicon semiconductors, it is expected to provide a low-cost and compact solution for various near-infrared receiver devices such as these for Internet of Things (IoT) applications.
“…The n+ regions were formed by thermal diffusion from the deposited PSG (phosphosilicate glass) films, and the p+ regions were formed by boron ion implantation. The PD arrays are formed by the Bosch process using deep reactive ion etching (Deep RIE) [32][33] [34]. Its trench width is 20 µm at the top of the chip and 15 µm at its bottom, and its silicon substrate thickness is 540 µm.…”
In this paper, we report a method of increasing the sensitivity of a silicon near-infrared sensor. The sensor is realized by forming multiple trench-type photodiodes in a silicon chip. The trench photodiodes can be formed using conventional semiconductor fabrication equipment. The device structure allows the depletion layer to be spread over the entire sensor chip even at a bias voltage of 10 V or less. The sensor chip can thereby extend the collection area of photoelectrons to the maximum. At a chip thickness of 540 µm, the conversion efficiency for near-infrared wavelengths between 940 and 1020 nm is more than 80% at room temperature. In addition, the electrical characteristics and response performance of the fabricated 2.4 mm × 2.4 mm test chips are reported. Since the proposed method can achieve a high conversion efficiency at low voltage without cooling in silicon semiconductors, it is expected to provide a low-cost and compact solution for various near-infrared receiver devices such as these for Internet of Things (IoT) applications.
The Bistable Spherical Compliant Mechanisms (BSCM) is a novel device capable of large, repeatable, out-of-plane motion, characteristics that are somewhat difficult to achieve with surface micro-machined MEMS. An improved pseudo-rigid-body model to predict the behavior of the BSCM is presented. The new model was used to analyze seven different versions of the device, each with a different compliant joint length. The new model, which adds torsion, is compared with a Finite-Element beam model. The new model more closely approximates the results yielded by FEA than previous models used to analyze the BSCM. Future work is needed to quantify stress-stiffening interactions between bending and torsion. Both FEA and the current model show that increasing the length of the compliant segment decreases the amount of force required to actuate the device.
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