BOOM: Enabling mobile memory based low-power server DIMMs

Yoon, Kyoungro; Chang,; Muralimanohar,; Ranganathan,

doi:10.1109/isca.2012.6237003

Cited by 28 publications

(40 citation statements)

References 12 publications

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“…As a result, DRAM page activation energy accounts for a significant fraction of dynamic memory energy (Figure 1), corroborating prior work [1,46,57] and demonstrating that row buffer locality is not fully exploited in server CMPs and calling for techniques to maximize row buffer hits.…”

Section: Dram Row Buffer Locality In Serverssupporting

confidence: 85%

“…Based on the observation that off-chip memory bandwidth is often not utilized, prior work has either applied voltage frequency scaling to the memory controller and frequency scaling to the memory interface and devices [6,7], or proposed using low-power, low-speed memory interfaces [34,57]. However, emerging many-core processors saturate memory bandwidth [13,17,32], thereby mandating high-speed memory interfaces to maximize perpin available bandwidth.…”

Section: Related Workmentioning

confidence: 99%

“…In practice, we find that this rarely happens as accesses to any given page are interleaved with a stream of accesses to other pages, hence destroying DRAM row buffer locality [1,46,47,57]. Keeping pages open and prioritizing accesses to an open page helps only to some extent, as accesses to different blocks within a page are often separated by a distance that is beyond the reach of the memory controller's scheduling window or occur in a datadependent fashion [51].…”

Section: Introductionmentioning

confidence: 99%

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BuMP: Bulk Memory Access Prediction and Streaming

Volos¹,

Picorel²,

Falsafi³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As the industry moves to lean-core server processors, the energy bottleneck is shifting toward main memory as a chief source of server energy consumption in modern datacenters. Maximizing the energy efficiency of today's DRAM chips and interfaces requires amortizing the costly DRAM page activations over multiple row buffer accesses.This work introduces Bulk Memory Access Prediction and Streaming, or BuMP. We make the observation that a significant fraction (59-79%) of all memory accesses fall into DRAM pages with high access density, meaning that the majority of their cache blocks will be accessed within a modest time frame of the first access. Accesses to high-density DRAM pages include not only memory reads in response to load instructions, but also reads stemming from store instructions as well as memory writes upon a dirty LLC eviction. The remaining accesses go to low-density pages and virtually unpredictable reference patterns (e.g., hashed key lookups). BuMP employs a low-cost predictor to identify high-density pages and triggers bulk transfer operations upon the first read or write to the page. In doing so, BuMP enforces high row buffer locality where it is profitable, thereby reducing DRAM energy per access by 23%, and improves server throughput by 11% across a wide range of server applications.

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Section: Dram Row Buffer Locality In Serverssupporting

confidence: 85%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

BuMP: Bulk Memory Access Prediction and Streaming

Volos¹,

Picorel²,

Falsafi³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

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“…It relies on the programmer to separate application data into vulnerable or tolerant data. Less reliable mobile DIMMs have been proposed [48,49] as a replacement for ECC DIMMs in servers to improve energy efficiency.…”

Section: B Related Workmentioning

confidence: 99%

Characterizing Application Memory Error Vulnerability to Optimize Datacenter Cost via Heterogeneous-Reliability Memory

Luo

Govindan

Sharma

et al. 2014

2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks

137

150

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Abstract-Memory devices represent a key component of datacenter total cost of ownership (TCO), and techniques used to reduce errors that occur on these devices increase this cost. Existing approaches to providing reliability for memory devices pessimistically treat all data as equally vulnerable to memory errors. Our key insight is that there exists a diverse spectrum of tolerance to memory errors in new data-intensive applications, and that traditional one-size-fits-all memory reliability techniques are inefficient in terms of cost. For example, we found that while traditional error protection increases memory system cost by 12.5%, some applications can achieve 99.00% availability on a single server with a large number of memory errors without any error protection. This presents an opportunity to greatly reduce server hardware cost by provisioning the right amount of memory reliability for different applications.Toward this end, in this paper, we make three main contributions to enable highly-reliable servers at low datacenter cost. First, we develop a new methodology to quantify the tolerance of applications to memory errors. Second, using our methodology, we perform a case study of three new dataintensive workloads (an interactive web search application, an in-memory key-value store, and a graph mining framework) to identify new insights into the nature of application memory error vulnerability. Third, based on our insights, we propose several new hardware/software heterogeneous-reliability memory system designs to lower datacenter cost while achieving high reliability and discuss their trade-offs. We show that our new techniques can reduce server hardware cost by 4.7% while achieving 99.90% single server availability.

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“…First, PCM based main memory tends to be big to support large scale parallelizable workloads [19], which limits the budget available to a DIMM. Second, recent years have seen the need for low power DIMMs [13,29].…”

Section: Dimm Power Budgetmentioning

confidence: 99%

FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory

Jiang

Zhang

Childers

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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As a promising nonvolatile memory technology, Phase Change Memory (PCM) has many advantages over traditional DRAM. Multilevel Cell PCM (MLC) has the benefit of increased memory capacity with low fabrication cost. Due to high per-cell write power and long write latency, MLC PCM requires careful power management to ensure write reliability. Unfortunately, existing power management schemes applied to MLC PCM result in low write throughput and large performance degradation.In this paper, we propose Fine-grained write Power Budgeting (FPB) for MLC PCM. We first identify two major problems for MLC write operations: (i) managing write power without consideration of the iterative write process used by MLC is overly pessimistic; (ii) a heavily written (hot) chip may block the memory from accepting further writes due to chip power restrictions, although most chips may be available. To address these problems, we propose two FPB schemes. First, FPB-IPM observes a global power budget and regulates power across write iterations according to the step-down power demand of each iteration. Second, FPB-GCP integrates a global charge pump on a DIMM to boost power for hot PCM chips while staying within the global power budget. Our experimental results show that these techniques achieve significant improvement on write throughput and system performance. Our schemes also interact positively with PCM effective read latency reduction techniques, such as write cancellation, write pausing and write truncation.

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BOOM: Enabling mobile memory based low-power server DIMMs

Cited by 28 publications

References 12 publications

BuMP: Bulk Memory Access Prediction and Streaming

BuMP: Bulk Memory Access Prediction and Streaming

Characterizing Application Memory Error Vulnerability to Optimize Datacenter Cost via Heterogeneous-Reliability Memory

FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory

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