Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams

A new methodology for designing Totally Self-Checking combinational circuits through the encoding of the primary outputs with the parity code is presented. The parity code requires that each fault modifies an odd number of outputs for providing its detection, that is, each fault has to be oddly observable. The proposed methodology for fulfilling such a constraint consists of a post-synthesis modification of fault observability through either the introduction of an auxiliary output for the examined network node or the replication of the investigated node. A cost evaluation function allows us to select the most convenient solution in terms of overhead and the final 100% TSC circuit

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Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks

Bolchini

Salice²,

Sciuto³

Proceedings Great Lakes Symposium on VLSI

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ZEPHCAD and FLORA: logic synthesis for control and datapath

Sato

Yamazaki²,

Fujita³

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

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A technology mapping method based on perfect and semi-perfect matchings

Crastes

Sakouti

Saucier

1991

Proceedings of the 28th Conference on ACM/IEEE Design Automation Conference - DAC '91

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Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams

Cited by 3 publications

References 11 publications

Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks

Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks

ZEPHCAD and FLORA: logic synthesis for control and datapath

A technology mapping method based on perfect and semi-perfect matchings

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