We have developed multi-level logic minimization programs using Binary Decision Diagram (BDD). Here we p m t variable ordering methods of BDD. The variable ordering algorithm for twolevel circuits is based on cover patterns and selects most binate variables first. and the one for multi-level circutis is based on depth first traveme of circuits. In both cases. the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.
Amrubicin is a novel synthetic 9-aminoanthracycline derivative and is converted enzymatically to its C-13 hydroxy metabolite, amrubicinol, whose cytotoxic activity is 10-100 times that of amrubicin. We aimed to determine the maximum tolerated dose (MTD) of amrubicin and to characterize the pharmacokinetics of amrubicin and amrubicinol in previously treated patients with refractory or relapsed lung cancer. The 15 patients were treated with amrubicin intravenously at doses of 30, 35, or 40 mg/m(2) on three consecutive days every 3 weeks for a total of 43 courses. Neutropenia was the major toxicity (grade 4, 67%). The MTD was 40 mg/m(2), with the specific dose-limiting toxicities being grade 4 neutropenia persisting for >4 days, febrile neutropenia, or grade 3 arrhythmia in the three patients treated at this dose. A patient with non-small-cell lung cancer showed a partial response, and ten individuals experienced a stable disease. The area under the plasma concentration versus time curve (AUC) for amrubicin and that for amrubicinol increased with amrubicin dose. The amrubicin AUC was significantly correlated with the amrubicinol AUC. The recommended phase II dose of amrubicin for patients with lung cancer refractory to standard chemotherapy is thus 35 mg/m(2) once a day for three consecutive days every 3 weeks.
This paper presents a new LP based optimal cell selection method. Optimal cell selection is useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle both setup and hold time constraints. We also make an efficient initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it reduces the clock cycle of a manual designed 13k-transistor chip by 17% without any increase of area.
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