Bond-based design for MMW CMOS circuit optimization

Abstract

IntroductionRecently, millimeter-wave (MMW) applications have attracted much attention for their use in ultrahigh-speed wireless communication utilizing the unlicensed 60GHz band. In particular, advanced MMW CMOS circuits with all the circuit elements including the digital circuit on a single chip are potentially realizable, reducing the fabrication cost and power consumption of the MMW circuit to levels allowing their use in consumer products. Thus, MMW CMOS circuits are expected to become more widespread in consumer products in the near future. The MMW CMOS circuit must achieve high performance while substantially reducing the development time of products to satisfy the increasing demand for wireless systems in digital home appliances.However, the design of the MMW CMOS circuit is generally more difficult than that of microwave circuits. The energy loss of the passive components in an MMW CMOS circuit is significant, and it is necessary to reduce this loss. To minimize the loss of the matching circuit, size optimization of the passive components is required. Additionally, network impedance is also dependent on the size of the passive components. Nevertheless, optimization of the passive component network taking loss into account is generally a complicated task. Therefore, computer-based optimization is effective for MMW circuits that contain lossy passive components. Several optimization techniques for microwave CMOS circuits have been already reported [1][2][3]. In contrast to microwave CMOS circuits, since MMW CMOS circuits are strongly affected by the parasitic inductance and resistance of the metal due to the short wavelength, no wiring of devices are easily estimated. The widely used method of layout parameter extraction (LPE) cannot be used to accurately estimate parasitic inductance. Because of the skin effect, the accurate estimation of parasitic resistance is also difficult. Consequently, there is a discrepancy between the results of circuit-level analysis and layout, and this makes circuit-level optimization less accurate. To overcome these issues, we propose bond-based design for the MMW CMOS circuits. Bond-Based DesignIn the bond-based design, the matching network based on the modeled transmission line (TL) is adopted so that all the wirings are replaced with TLs. Here, all the devices including TLs are bonded without insufficiently characterized components to compose a circuit as if atoms form a molecule with chemical bonds, as shown in Fig. 1. To realize the bond-based design, device elements are designed so that all devices are bonded smoothly. Consequently, connecting ports of a MOSFET and a capacitor have the same 978-1-4244-2642-3/08/$25.00 ©2008 IEEE cross sections as those of TLs. With bond-based design, no discrepancy between the circuit-optimization results and post-layout simulation occurs. Furthermore, layout generation becomes easier when the bond-based design is adopted because no routing is required. For practical application of the bondbased design, we propose the PREMICS, which is a...

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98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits

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