Body width dependence of subthreshold slope and on-current in GaAsSb/InGaAs double-gate vertical tunnel FETs

Ohashi, Keisuke; Fujimatsu, Motohiko; Iwata, Shinjiro; Miyamoto, Yasuyuki

doi:10.7567/jjap.54.04df10

Cited by 12 publications

(13 citation statements)

References 29 publications

(31 reference statements)

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“…InAs-GaAs GAA-TFET results has been analyzed with help of Silvaco-TCAD Tool. Band to Band Tunneling (BTBT) non-local model is considered for tunneling of carriers at the junctions [11]- [13]. This section covers energy band profile analysis, DC Characteristics and analog/RF performance analysis.…”

Section: Reults and Discussionmentioning

confidence: 99%

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Performance Analysis of InAs-GaAs Gate-all-around Tunnel Field Effect Transistors (GAA-TFET) for Analog/ RF applications

Saravanan¹,

Parthasarathy²,

Ramkumar³

2022

J. Phys.: Conf. Ser.

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The purpose of this study to explore the performance of InAs-GaAs Gate-all-around (GAA) tunnelling field effect transistors (TFETs) in analogue and RF applications. The TCAD tool was used to assess the device’s overall performance. In order to achieve the InAs-GaAs channel design, the suggested TFET features a gate oxide made of SiO2 near the drain and HfO2 near the source region. As a result of the hetero dielectric gate oxide being used, the tunnelling width at junction between drain and channel (JDC) and junction between source and channel (JSC) is reduced, and the ON-current at the drain-channel junction is increased (ION). Device simulations have revealed that the SiO2-HfO2 gate dielectric has a low off-current (IOFF) of 2.27 x 10−17 A/m, a high enhanced ION of 7.39 x 10−6 A/m. At the time of operation, the sub-threshold swing (SS) was 16.8 mV/dec. Because of its low power consumption, the device could potentially be a better choice for power management circuits used in energy harvesting applications, according to the findings.

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Section: Reults and Discussionmentioning

confidence: 99%

“…Throughout, the simulations were performed at room temperature. It has a ION of 7.39 x 10 -6 A/m, IOFF of 2.27 x 10-17 and ION/IOFF value is 3.25 x10 11 . The minimum point SS of 16.8 mV/dec and the maximum cut-off frequency of 700 GHz.…”

Section: Discussionmentioning

confidence: 99%

Performance Analysis of InAs-GaAs Gate-all-around Tunnel Field Effect Transistors (GAA-TFET) for Analog/ RF applications

Saravanan¹,

Parthasarathy²,

Ramkumar³

2022

J. Phys.: Conf. Ser.

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“…This can be explained based on the fact short-channel effects such as DIBL and charge sharing play a dominant role as gate length scale down. 2,4,31 Therefore, off-state current increases significantly. Figure 3 (b) shows the plot for switching state current ratio and subthreshold slope as a function of different gate length.…”

Section: -5mentioning

confidence: 99%

A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

2016

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In this paper, a silicon–on–insulator (SOI) p–n–p–n tunneling field–effect transistor (TFET) with a silicon doped hafnium oxide (Si:HfO2) ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band–to–band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3) and strontium bismuth tantalate (SrBi2Ta2O9) provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p–n–p–n SOI TFET, the on–state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS) is effectively reduced. The simulation results of Si:HfO2 ferroelectric p–n–p–n SOI TFET show significant improvement in transconductance (∼9.8X enhancement) at high overdrive voltage and average subthreshold slope (∼35% enhancement over nine decades of drain current) at room temperature, indicating that this device is a promising candidate to strengthen the performance of p–n–p–n and conventional TFET for a switching performance.

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“…[1][2][3][4][5] To push the scaling limit of silicon CMOS technology that has supported the evolution of LSI, devices with steep switching have been studied recently. [6][7][8][9][10][11] Among them, tunnel field-effect transistors (TFETs) have been most extensively studied, both experimentally [12][13][14][15][16][17][18][19][20] and theoretically. [21][22][23][24][25][26][27] Most of those TFETs were designed for realizing larger on-currents, smaller off-currents, and steep subthreshold slopes.…”

Section: Introductionmentioning

confidence: 99%

Simulation study of short-channel effects of tunnel field-effect transistors

Fukuda

Asai

Hattori

et al. 2018

Jpn. J. Appl. Phys.

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Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal–oxide–semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

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Body width dependence of subthreshold slope and on-current in GaAsSb/InGaAs double-gate vertical tunnel FETs

Cited by 12 publications

References 29 publications

Performance Analysis of InAs-GaAs Gate-all-around Tunnel Field Effect Transistors (GAA-TFET) for Analog/ RF applications

Performance Analysis of InAs-GaAs Gate-all-around Tunnel Field Effect Transistors (GAA-TFET) for Analog/ RF applications

A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

Simulation study of short-channel effects of tunnel field-effect transistors

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