BLAM: a high-performance routing algorithm for virtual cut-through networks

Thottethodi, Mithuna; Lebeck, Alvin R.; Mukherjee, S.

doi:10.1109/ipdps.2003.1213133

Cited by 14 publications

(5 citation statements)

References 32 publications

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“…Sowmya et al in [4]he attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remains on that itself to get a good control over the network. This paper is based on the hardware coding which will give a great impact on the latency issue as the hardware itself will be designed according to the need.…”

Section: A Generic Router Architecturementioning

confidence: 99%

VLSI Based Robust Router Architecture

Sowmya¹,

Shireesha²,

Swetha³

et al. 2016

IJSR

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Abstract:In this paper, we introduce networking solution by using VLSI architecture techniques to router design for networking system to provide control over the network. We attempts to overcome latency and time reduction issue and can provide multipurpose networking router by means of verilog and it was synthesized in Xilinx 13.2 version, simulated Modelsim 10.0 version. The approach enables the router to process mul-tiple incoming IP packets with different versions of protocols simultaneously, e.g. for IPv4 and IPv6.

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Section: A Generic Router Architecturementioning

confidence: 99%

VLSI Based Robust Router Architecture

Sowmya¹,

Shireesha²,

Swetha³

et al. 2016

IJSR

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“…The approach will results in increased switching speed of routing per packet for both current trend protocols, which we believe would result in considerable enhancement in networking systems. M. Sowmya et al in [4]he attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remains on that itself to get a good control over the network. This paper is based on the hardware coding which will give a great impact on the latency issue as the hardware itself will be designed according to the need.…”

Section: A Generic Router Architecturementioning

confidence: 99%

Implementation of VLSI Based Robust Router Architecture

2016

IJSR

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“…Dynamically allocated buffer structured was proposed in [11]. DAMQ with self compacting buffers [12], FCCB [13], VC allocation on traffic condition [14], Chaos router [15], BLAM routing algorithm [16], Geyser 1 [17] are also discussed in literature. Some power aware models are discussed in [18], [19], [20].…”

Section: Literature Surveymentioning

confidence: 99%

Segmented Buffer for NOC Router

Debbarma¹,

Pradhan²

2015

IJMO

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Abstract-As the number of transistors in a single chip is increasing day by day, SoC is a very popular choice among the developers as it gives more speed and functionality. The IPs in the SoCs can be from different vendors and may be used for a third party for manufacturing a chip. For effective communication among the IPs or more commonly Cores, an in built network structure called Network on Chip (NOC) has been developed over the years and different versions of NOCs are available in the present day. This paper proposes a segmented buffer structure for NOC router for effective utilization of the NOC buffers.

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BLAM: a high-performance routing algorithm for virtual cut-through networks

Abstract: Abstract

Cited by 14 publications

References 32 publications

VLSI Based Robust Router Architecture

VLSI Based Robust Router Architecture

Implementation of VLSI Based Robust Router Architecture

Segmented Buffer for NOC Router

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