Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files

Singh, Rahul; Hong, Gi-Moon; Kim, Suhwan

doi:10.1109/tcsi.2012.2220457

Cited by 7 publications

(4 citation statements)

References 29 publications

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“…Rahul Singh, Gi-Moon hong, Sulwan Kim [2] present new footer voltage feedforward domino (FVFD) and static-switching pulse domino (SSPD) designs for dynamic multiplexers. Both improve noise tolerance, and both reduce the switching power by limiting the voltage swing on the large bitline capacitance through the introduction of dual dynamic nodes.…”

Section: Literature Surveymentioning

confidence: 99%

CMOS Form of Wallace Range Exploitation Domino Logic Full Adder

Kolhe¹,

Gokhale²,

thakur³

2014

IOSRJVSP

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Section: Literature Surveymentioning

confidence: 99%

CMOS Form of Wallace Range Exploitation Domino Logic Full Adder

Kolhe¹,

Gokhale²,

thakur³

2014

IOSRJVSP

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“…Due to its high speed, wide fan-in dynamic logic OR gate has always been a preferred choice for high speed register¯le structures over the static logic. 1 However dynamic logic circuits inherently su®er from low noise immunity. 2 Furthermore, the wide fan-in dynamic logic circuit causes a large amount of leakage during the OFF state (when all the inputs to gate are logic \0").…”

Section: Introductionmentioning

confidence: 99%

“…1 Register¯les are an integral part of such processors. They are used almost in each clock cycle, as in order to execute each instruction data should be read or written to the register¯le.…”

Section: Introductionmentioning

confidence: 99%

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Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design

Mahor

Pattanaik

2015

J CIRCUIT SYST COMP

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Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with e®ective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the e®ective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.

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Design of efficient QCA multiplexers

Cocorullo

Corsonello

Frustaci

et al. 2015

Circuit Theory & Apps

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A new methodology to realize efficient multiplexers using quantum-dot cellular automata (QCA) is presented in this paper. The novel designs here demonstrated fully exploit the intrinsic logic capabilities of the basic building block in the QCA domain: the Majority Gate. An efficient logic formulation is derived for the 4:1 multiplexing function that can be recursively applied to the realization of multiplexers with any fan-in, by adding in the worst-case path only one level of Majority Gate for each input doubling. A 16:1 multiplexer designed by applying the proposed recursive approach requires less than 1600 cells and consumes only 12 clock phases to complete the operation. INTRODUCTIONRecently the emerging technology based on quantum-dot cellular automata (QCA) has received a great deal of attention, and several solutions have been proposed to design efficient logic circuits, such as multiplexers [1-3], adders [4][5][6][7][8][9][10][11], multipliers [12-18] and comparators [19][20][21][22][23][24][25][26].The QCA nanostructure originally demonstrated in [27] uses a square cell with four quantum dots and two free electrons as the basic element to realize both logic structures and interconnections. The free electrons can tunnel through the dots within the cell, but, owing to Coulombic repulsion, they can lead to only two possible stable states, also named polarizations, that are associated with the binary states 1 and 0. Even though adjacent cells interact through electrostatic forces and tend to align their polarizations, QCA cells do not have intrinsic data flow directionality. The latter is provided by means of four clock signals clk x (with x ranging from 0 to 3), shifted by 90°from each other, that are progressively associated to the cells within a QCA design [28,29]. This clock scheme, named the zone clocking scheme, makes the QCA designs intrinsically pipelined, because each clock zone behaves like a D-latch.The fundamental logic gates inherently available within the QCA technology are the inverter and the majority gate (MG); non-elementary digital modules are designed combining instances of these basic gates and exploiting an efficient zone clocking scheme . The design of complex gates, such as multiplexers (MUXes), is not actually straightforward, and proper strategies have to be adopted at both logic and layout levels to improve performance and area behaviors.Large fan-in multiplexers (i.e. larger than 4:1) are crucial as fundamental blocks in several popular applications; few examples are the realization of lookup tables for special function units and the decoders in memory circuits [30][31][32][33][34][35][36]. This paper is focused on the design of efficient QCA-based large fan-in MUXes and proposes a novel approach that smartly exploits the majority logic function

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Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files

Cited by 7 publications

References 29 publications

CMOS Form of Wallace Range Exploitation Domino Logic Full Adder

CMOS Form of Wallace Range Exploitation Domino Logic Full Adder

Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design

Design of efficient QCA multiplexers

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