Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems

Thörnberg, Benny; Palkovic, Martin; Hu, Qubo; Olsson, Leif; Kjeldsberg, Per Gunnar; O’Nils, Mattias; Catthoor, Francky

doi:10.1109/tcad.2006.884569

Cited by 9 publications

(5 citation statements)

References 28 publications

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“…One optimization that is explored is buffer retiming, which is depicted in Figure 7 [25]. The objective is to move buffers such that the behavior of the whole system does not change and such that the total size of all buffers is minimized.…”

Section: Space-time Optimizationmentioning

confidence: 99%

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C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation

Lawal

O’Nils

Thörnberg

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Section: Space-time Optimizationmentioning

confidence: 99%

“…For example, in Figure 7A the delay is placed after operation B the width of the buffer is 12, and when moved to the signal width is reduce to 8. The behavior of the system is unchanged but the buffer size is reduced by 33% [25]. Other optimizations that are explored are sharing of buffers between tasks and buffer elimination.…”

Section: Space-time Optimizationmentioning

confidence: 99%

C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation

Lawal

O’Nils

Thörnberg

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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“…The research which includes memory architecture [10], estimation [11], optimization [12] and allocation [2] have been developed into a set of design tools called IMEM that support designers in implementing efficient memory subsystem so that designers can focus on developing the video processing algorithm.…”

Section: Architecturementioning

confidence: 99%

“…We improve design performance through a memory architecture optimized for real-time video processing systems [2], [12] and automatically generate place and route constraints. Because video processing applications are data dominated, the place and route process is constrained to allocate design logic as close to the memory as possible thus minimizing total area occupied by the design.…”

Section: Introductionmentioning

confidence: 99%

Power-aware automatic constraint generation for FPGA based real-time video processing systems

2007

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The introduction of embedded DSP blocks and embedded memory has made FPGAs an attractive architecture for implementation of real-time video processing systems. The big bottle neck of the FPGA compared to other programmable architectures is the complex programming model. This paper presents an automatic generation of placement and routing constraints for FPGA implementation of real-time video processing systems as one step to automate the programming model. The constraint generator targets lower power consumption, better resource utilization and reduced development time. Results show that a 28 % reduction in dynamic power can be achieved using the proposed approach over traditional logic to memory mapping.

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“…A design methodology for mapping computer vision algorithm onto an FPGA through the use of coarse grain reconfigurable data flow graph was discussed in detail in [5] and [13]. The pros and cons of FPGA technology and its suitability for computer vision task were discussed in detail in [3] and its optimization in [12] and [14]. The large amount of data generated by a vision sensor node requires a great deal of energy for processing and transmission bandwidth compared to other types of sensor networks.…”

Section: Introductionmentioning

confidence: 99%

Exploration of target architecture for a wireless camera based sensor node

et al. 2010

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Abstract. The challenges associated with wireless vision sensor networks are low energy consumption, less bandwidth and limited processing capabilities. In order to meet these challenges different approaches are proposed. Research in wireless vision sensor networks has been focused on two different assumptions, first is sending all data to the central base station without local processing, second approach is based on conducting all processing locally at the sensor node and transmitting only the final results. Our research is focused on partitioning the vision processing tasks between Senor node and central base station. In this paper we have added the exploration dimension to perform some of the vision tasks such as image capturing, background subtraction, segmentation and Tiff Group4 compression on FPGA while communication on microcontroller. The remaining vision processing tasks i.e. morphology, labeling, bubble remover and classification are processed on central base station. Our results show that the introduction of FPGA for some of the visual tasks will result in a longer life time for the visual sensor node while the architecture is still programmable. I. INTRODUCTIONTypically Vision Sensor Nodes (VSN) in Wireless Vision Sensor Networks (WVSN) consists of a camera for acquiring images, a processor for local image processing and a transceiver for communicating the results to the central base station. Due to the technological development in image sensors, sensor networking, distributed processing, low power processing and embedded systems smart camera networks can perform complex tasks using limited resources such as batteries, a wireless link and with a limited storage facility. Such camera based networks could easily be installed in out-doors areas where there is a limited availability of power, where access is difficult and it is inconvenient to modify the locations of the nodes or frequently change the batteries. VSN have been designed and implemented on microcontroller and microprocessor [1,4]. Often these solutions have high power consumption and moderate processing capabilities. Due to rapid development in the semiconductor technology, the single chip capacity of Field Programmable Gate Array (FPGA) increases greatly while its power consumption decreases tremendously [15]. Presently FPGA chips consist of many cores which makes it ideal candidate for the designing of VSN. As VSN needs to be capable of performing complex image processing such as image compression, which needs a lot of processing. High processing requirement is increased for an increased image size. Attention must be paid to the hardware/software co-design strategy to meet both processing and power requirements of VSN [8]. In [9] the authors designed a novel VSN based on a low cost, low power FPGA plus microcontroller System on Programmable Chip (SOPC). The authors in [10] have implemented a computer vision algorithm in hardware. They have provided a comparison of hardware and software implemented system using the same algorithm. It is c...

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Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems

Cited by 9 publications

References 28 publications

C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation

C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation

Power-aware automatic constraint generation for FPGA based real-time video processing systems

Exploration of target architecture for a wireless camera based sensor node

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