Bit-slice logic interleaving for spatial multi-bit soft-error tolerance

George, Nishant; Elks, Carl; Johnson, B.W.; Lach, John

doi:10.1109/dsn.2010.5544920

Cited by 4 publications

(1 citation statement)

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“…George et al modeled spatial MBFs using a fault injection methodology [15]. George et al examined interleaving as a potential remedy to sMBFs in combinational logic [14], and Szafaryn et al examined the overheads associated with multi-bit fault protection [37]. Suh et al introduced the PARMA framework to compute the MTTF of caches from single-bit and temporal multi-bit faults [36].…”

Section: Existing Multi-bit Remediation Techniquesmentioning

confidence: 99%

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Wilkening

Sridharan

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Reliability is an important design constraint in modern microprocessors, and one of the fundamental reliability challenges is combating the effects of transient faults. This requires extensive analysis, including significant fault modeling to allow architects to make informed reliability tradeoffs. Recent data shows that multi-bit transient faults are becoming more common, increasing from 0.5% of SRAM faults in 180nm to 3.9% in 22nm, and are predicted to be even more prevalent in smaller technology nodes. Therefore, accurately modeling the effects of multi-bit transient faults is increasingly important to the microprocessor design process.Architecture vulnerability factor (AVF) analysis is a method to model the effects of single-bit transient faults. In this paper, we propose a method to calculate AVFs for spatial multi-bit transient faults (MB-AVFs) and provide insights that can help reduce the impact of these faults. First, we describe a novel multi-bit AVF analysis approach for detected, uncorrected errors (DUEs) and show how to measure DUE MB-AVFs in a performance simulator. We then extend our approach to measure SDC MB-AVFs. We find that MB-AVFs are not derivable from single-bit AVFs. We also find that larger fault modes have higher MB-AVFs. Finally, we present a case study on using MB-AVF analysis to optimize processor design, yielding SDC reductions of 86% in a GPU vector register file.

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Section: Existing Multi-bit Remediation Techniquesmentioning

confidence: 99%