Bit-serial dual basis systolic multipliers for GF(2/sup m/)

Fenn, S.T.J.; Benaïssa, Mohammed; Taylor, David J.

doi:10.1109/iscas.1995.523814

Cited by 4 publications

(10 citation statements)

References 7 publications

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“…Table 1 depicts comparing results of the proposed multiplier in Fig. 3 and bit-parallel systolic multipliers in [6,9]. Both related multipliers have the same hardware requirements, latencies, computation times, and unidirectional data flow.…”

Section: Bit-parallel Systolic Multiplier Over Gf(2 M )mentioning

confidence: 99%

“…For the polynomial basis, it is difficult to compute an inverse using the multiply-square algorithm since the number of multiplication is too great. A dual basis multiplier in [9] for each multiply-square computations needs extra logical operations to perform the basis conversion. The proposed bit-parallel systolic multiplier has low-complexity architecture as compared with two related multipliers.…”

Section: Bit-parallel Systolic Multiplier Over Gf(2 M )mentioning

confidence: 99%

“…However, Lee's multiplier [8] has two major shortcomings. First, if no such AOP is existed in GF(2 m ), then the implemented Lee's multiplier for such fields needs more circuit complexity than conventional systolic multipliers [7,9], because its redundant presentation is required with a large length of n bits. For instance, the field is constructed from x 3 +x+1, each field element is represented by a length of 7 bits.…”

Section: Bit-parallel Systolic Multiplier Over Gf(2 M )mentioning

confidence: 99%

“…Generally, array algorithms are classified as least-significant bit first and most-significant bit first schemes. Recently, several systolic-type multipliers based on dual basis were proposed [9][10]. Above mentioned multipliers have common characteristics, those are by using Horner's rule to realize regular circuit deigns and independent on a particular choice of m for GF(2 m ).…”

Section: Introductionmentioning

confidence: 99%

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New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations

Lee

Chiou²

2008

J Sign Process Syst Sign Image Video Technol

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A new bit-parallel systolic multiplier over GF (2 m ) under the polynomial basis and normal basis is proposed. This new circuit is constructed by m 2 identical cells, each of which consists of one two-input AND gate, one three-input XOR gate and five 1-bit latches. Especially, the proposed architecture is without the basis conversion as compared to the well-known multipliers with the redundant representation. With this proposed multiplier, a parallel-in parallel-out systolic array has also been developed for computing inversion and division over GF(2 m ). The proposed architectures are well suited to VLSI systems due to their regular interconnection pattern and modular structure.

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Section: Bit-parallel Systolic Multiplier Over Gf(2 M )mentioning

confidence: 99%

Section: Bit-parallel Systolic Multiplier Over Gf(2 M )mentioning

confidence: 99%

Section: Bit-parallel Systolic Multiplier Over Gf(2 M )mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations

Lee

Chiou²

2008

J Sign Process Syst Sign Image Video Technol

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“…Furthermore since each basic cell is only connected with its neighboring cells, signals can be propagated at a high clock speed. There are systolic multipliers using a polynomial basis [7,8,10,11,12,13,15] and a dual basis [9]. A bit parallel systolic multiplier in [8] has a comparable or better longest path delay than the multipliers in [7,9,10].…”

Section: Introductionmentioning

confidence: 99%

A low complexity and a low latency bit parallel systolic multiplier over GF(2/sup m/) using an optimal normal basis of type II

Kwon

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.

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Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF (2 m ) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m + 1 and the basic cell of our circuit design needs 5 latches (flip-flops). On the other hand, most of other multipliers of the same type have latency 3m and the basic cell of each multiplier needs 7 latches. Comparing the gates areas in each basic cell, we find that the hardware complexity of our multiplier is 25 percent reduced from the multipliers with 7 latches.

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