New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations

Abstract

A new bit-parallel systolic multiplier over GF (2 m ) under the polynomial basis and normal basis is proposed. This new circuit is constructed by m 2 identical cells, each of which consists of one two-input AND gate, one three-input XOR gate and five 1-bit latches. Especially, the proposed architecture is without the basis conversion as compared to the well-known multipliers with the redundant representation. With this proposed multiplier, a parallel-in parallel-out systolic array has also been developed for computing inversion and division over GF(2 m ). The proposed architectures are well suited to VLSI systems due to their regular interconnection pattern and modular structure.

Efficient hardware structure for extended Euclidean‐based inversion over

“…The hardware consumption for the proposed structure consists of 2‐input XOR, NOT, 2‐input AND, 2‐input OR, D flip‐flop, 2‐to‐1 multiplexer, 4‐to‐1 multiplexer. The hardware resources in works [2, 9, 11, 13] and [4] achieve area complexity of O () and O ( mL ) (where, m and L are field size and digit size, respectively), respectively. Therefore, the hardware resources in these works are higher than those of the proposed structure.…”

“…In recent years, different hardware implementations of the field inversion over F 2 m are presented in literature [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. The works [2][3][4][5][6][7][8][9][10][11][12][13][14][15] are implemented in polynomial basis (PB). Several structures for the field inversion based on systolic architecture have been presented.…”

“…The architecture is based on the bit-serial multiplication algorithm and the modified extended Euclidean inversion algorithm proposed in [13]. In [9], a parallel-in parallel-out systolic array is developed for computing field inversion and division. The inversion operation in recent works [14][15][16][17][18][19][20] is implemented based on Itoh-Tsujii inversion algorithm (ITA) in PB.…”

Subquadratic space complexity Gaussian normal basis multipliers overGF(2m) based on Dickson–Karatsuba decomposition

“…Several hardware architectures for GNB multiplication using redundant presentation have been proposed in the literature. For example, we find bit-parallel architectures in [4][5][6], digit-serial and bit-serial architectures in [7,8] and scalable architectures in [9,10]. The GNB multiplication for even-type t shows self-dual NB multiplication, which is presented in [11].…”

An Efficient Pipelined Multiplicative Inverse Architecture for the AES Cryptosystem

“…The main drawback is the complexity of the VLSI implementation. Other possible approaches to deal with multiplicative inverse include using elliptic curve technique [4] and using polynomial bases [1]- [3], [11], [9]. The main advantage of such approaches is their suitability to VLSI architecture.…”