“…The hardware consumption for the proposed structure consists of 2‐input XOR, NOT, 2‐input AND, 2‐input OR, D flip‐flop, 2‐to‐1 multiplexer, 4‐to‐1 multiplexer. The hardware resources in works [2, 9, 11, 13] and [4] achieve area complexity of O () and O ( mL ) (where, m and L are field size and digit size, respectively), respectively. Therefore, the hardware resources in these works are higher than those of the proposed structure.…”