Biscuit: A Framework for Near-Data Processing of Big Data Workloads

Gu, Boncheol; Yoon, A. S.; Bae, Duck‐Ho; Jo, Inseong; Lee, Jin Young; Yoon, Jonghyun; Kang, Jeong‐Uk; Kwon, Moonsang; Yoon, Chanho; Cho, Sangyeun; Jeong, Jin Hee; Chang, Donghoon

doi:10.1109/isca.2016.23

Cited by 113 publications

(115 citation statements)

References 19 publications

Supporting

Mentioning

112

Contrasting

Unclassified

Order By: Relevance

“…A first group of related work can be classified as Near Data Processing (NDP) [16] to FPGA acceleration of large scale data [17], [18]. FastPath differs from the aforementioned approach by targeting OS code, rather than application code and by accelerating I/O requests to NVMe SSDs on FPGAs.…”

Section: Related Workmentioning

confidence: 99%

FastPath: Towards Wire-speed NVMe SSDs

Stratikopoulos¹,

Kotselidis²,

Goodacre³

et al. 2018

EasyChair Preprints

View full text Add to dashboard Cite

Abstract-The constant growth of data and its importance to drive Machine Learning and Big Data is pushing storage systems towards ever increasing I/O bandwidth and lower latency requirements. In recent years, the Non Volatile Memory Express (NVMe) standard has enabled SSD drives to deliver high I/O rates by allowing the storage to be connected directly via the fastest available interconnect to the processing chip. In parallel, the adoption of FPGAs in data centers is creating opportunities to accelerate various applications and/or Operating System (OS) operations. While, FPGAs in data centers have been connected via PCIe to mostly x86 servers, we have now also available heterogeneous SoCs with multi-cores and FPGAs integrated on the same die and connected by an onchip interconnect.In this paper, we present how to rethink and accelerate NVMe performance on heterogeneous SoC with integrated FPGAs providing a first research insight on the performance benefits of such an approach. We provide an analysis of the Linux block I/O layer and showcase the relationship between the system's performance and its I/O implementation. Consequently, we introduce an FPGA-based fast path which accelerates the access to the NVMe drive. Our comparative evaluation demonstrates that our FPGA-based FastPath achieves up to 71% lower latency and up to 5x higher I/O performance against the baseline system on a Zynq development board.

show abstract

Section: Related Workmentioning

confidence: 99%

FastPath: Towards Wire-speed NVMe SSDs

Stratikopoulos¹,

Kotselidis²,

Goodacre³

et al. 2018

EasyChair Preprints

View full text Add to dashboard Cite

show abstract

“…Floem [15] is a programming system that aims to accelerate NIC applications development by providing abstractions to ease NIC-offloading design. Biscuit [7] (a) Aggregated Throughput (b) Platform Power Consumption is a near-data processing framework. It allows developers to write data-intensive programs to be offloaded onto storage devices.…”

Section: Related Workmentioning

confidence: 99%

MBWU: Benefit Quantification for Data Access Function Offloading

Jian-shen

Kufeldt

Maltzahn

2019

Lecture Notes in Computer Science

View full text Add to dashboard Cite

The storage industry is considering new kinds of storage devices that support data access function offloading, i.e. the ability to perform data access functions on the storage device itself as opposed to performing it on a separate compute system to which the storage device is connected. But what is the benefit of offloading to a storage device that is controlled by an embedded platform, very different from a host platform? To quantify the benefit, we need a measurement methodology that enables apple-to-apple comparisons between different platforms. We propose a Media-based Work Unit (MBWU, pronounced "MibeeWu"), and an MBWU-based measurement methodology to standardize the platform efficiency evaluation so as to quantify the benefit of offloading. To demonstrate the merit of this methodology, we implemented a prototype to automate quantifying the benefit of offloading the key-value data access function.

show abstract

“…GPU accelerated computing has been proposed in the variety of fields such as deep learning, analytics, and engineering applications, offloading compute-intensive portions of the application to the GPU, while the remainder of the code still runs on the CPU [2,3]. In addition to FPGAs/GPUs, application-specific hardware accelerators are being integrated into platforms for widely used workloads such as compression [4], cryptography [5], big data [6], and deep learning [7].…”

Section: Introductionmentioning

confidence: 99%

“…1 illustrates the brief description of LZ4 compression algorithm. The token (6,4) describes that there are 6 bytes of uncompressed literals and 4 compressed data bytes. The offset value 5 represents that the literals, matched with previously compressed literals, have been appeared before the offset value.…”

Section: Introductionmentioning

confidence: 99%

Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression

Lee

Jang

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65 nm CMOS technology.

show abstract

Biscuit: A Framework for Near-Data Processing of Big Data Workloads

Cited by 113 publications

References 19 publications

FastPath: Towards Wire-speed NVMe SSDs

FastPath: Towards Wire-speed NVMe SSDs

MBWU: Benefit Quantification for Data Access Function Offloading

Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression

Contact Info

Product

Resources

About