Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65 nm CMOS technology.
In this paper, we propose the hardware architecture for high-speed transaction logging of forex trading system. In forex trading market, the trading volume of currencies is growing larger every year. In order to provide real-time processing of large volume and high availability service, we focused on the two types of the workload, where the bottleneck occurs, and conducted workload analysis. The bottleneck between the application server and the internal hard disk is caused by the overhead from storing the transaction logs, due to the bandwidth limitation of a hard disk. Our key idea is to suppress an overhead of the transaction logging through the compression of the transaction logs. Implementation result demonstrates the feasibility of our proposal for increasing the bandwidth through the log compression.
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