BiCMOS, a technology for high-speed/high-density ICs

Klose, H.; Zehner, B.; Wieder, A.W.

doi:10.1109/iccd.1989.63377

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Cited by 2 publications

(2 citation statements)

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“…In the second phase of the project the BICMOS2 (12,17,18) technology has been developed. The integration concept involves standard LDD MOS devices and self-aligned double-polysilicon bipolar devices.…”

Section: The Technologymentioning

confidence: 99%

BICMOS: From Dream to Reality

Josquin

Klose

1990

Esprit ’90

Self Cite

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Section: The Technologymentioning

confidence: 99%

BICMOS: From Dream to Reality

Josquin

Klose

1990

Esprit ’90

Self Cite

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“…The provisions for special functional units such as the cache, data path and internal memory are discussed. From this, we estimate speed, area and power consumption of a corresponding BiCMOS version based on the BiCMOS process described in [3].…”

Section: Introductionmentioning

confidence: 99%

BiCMOS approach for a RISC microprocessor

Pfaeffel

Heimsch

Reisch

et al. 1991

1991 IEEE International Symposium on Circuits and Systems (ISCAS)

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A concept for a BiCMOS implementation of a RISC microprocessor CPU is proposed. It is based on a CMOS implementation without architectural changes to maintain software compatib~ty. The circuit paths are analyzed and the provisions for special functional units such as the cache, data path and internal memory are derived. A significant performance gain --about factor 2.5 --is achieved with a limited number of bipolar current switches. BiCMOS permits the performance of ECL versions at a substantially lower power budget and area consumption by combining CMOS technology for memory cell arrays and the bulk of logic circuits with ECL in time-critical paths.

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BiCMOS, a technology for high-speed/high-density ICs

Cited by 2 publications

References 7 publications

BICMOS: From Dream to Reality

BICMOS: From Dream to Reality

BiCMOS approach for a RISC microprocessor

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