Bias Temperature Instability and Junction Temperature Measurement Using Electrical Parameters in SiC Power MOSFETs

Simulations and Measurements of Failure Modes in SiC Cascode JFETs under Short Circuit Conditions

“…SiC Cascode JFETs are a promising device technology that combines the gate oxide reliability of silicon MOSFETs with the fast switching of SiC MOSFETs [1,2]. SiC MOSFETs have been reported to have reduced gate oxide reliability compared to silicon MOSFETs and IGBTs [3][4][5][6][7], hence, the Cascode is attractive because it avoids the problem of increased interface trap density and fixed oxide traps in SiC/SiO2 MOS interfaces. The cascode is formed by connecting a low voltage (LV) silicon MOSFET between the gate-source terminals of a High Voltage (HV) SiC JFET so that the normally ON operation of the JFET is converted into normally OFF operation (as long as the MOSFET breakdown voltage is larger than the magnitude of the JFET pinch-off voltage).…”

Current Sharing of Parallel SiC MOSFETs under Short Circuit Conditions

“…The circuit diagram of the experimental set-up for the short circuit measurements is shown in Fig. 1 As expected, the peak short circuit current and short circuit energy increases with increased VGS due to the lower channel resistance [18,19]. Fig.…”

“…Studies of short circuit performance in SiC power modules have shown poor current sharing to be the primary cause of reduced robustness [9,14]. Even when devices are initially matched, phenomena like differential VTH drift from different rates of charge trapping of parallel connected SiC MOSFETs can cause small differences in VTH over the operational life of the device [15][16][17][18]. Furthermore, the short-circuit characteristics comprise of 2 phases namely (i) an initial rise in current (determined by the series inductance and threshold voltage) and (ii) the reduction of current due to resistive heating.…”

Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions

“…The results of the test described in Figure 14 are shown in Figure 15a for the 1.2 kV SiC Trench MOSFET, Figure 15b for the 1.2 kV SiC Planar MOSFET and Figure 15c for a silicon IGBT device. All the measurements in Figure 15 have been performed at a case temperature of 25 • C. The results for the SiC MOSFETs in Figure 15a,b show a slightly reduced short circuit charge as the V GS stress duration increases from 1 s to 100 s. The application of the pre-test V GS voltage causes a rise in V TH due to negative charge trapping [34], which subsequently causes a reduction in the short circuit current. Similar measurements performed on a 650 V silicon IGBT are shown in Figure 15c.…”