2012 International Electron Devices Meeting 2012
DOI: 10.1109/iedm.2012.6479121
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Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

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Cited by 41 publications
(35 citation statements)
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“…The AC transconductance (AC-g m ) technique was developed to examine the effect of border traps on the carrier transport, and it is assumed that the AC-g m dispersion reflects the border trap density in the gate dielectric. 8,15 Significant g m peak dispersion with respect to the different frequencies was observed, both for devices with RTCVD Si 3 N 4 ( Fig. 5(a)) and an ALD Al 2 O 3 ( Fig.…”
Section: Correlation Of Interface States/border Traps and Threshold Vmentioning
confidence: 98%
See 1 more Smart Citation
“…The AC transconductance (AC-g m ) technique was developed to examine the effect of border traps on the carrier transport, and it is assumed that the AC-g m dispersion reflects the border trap density in the gate dielectric. 8,15 Significant g m peak dispersion with respect to the different frequencies was observed, both for devices with RTCVD Si 3 N 4 ( Fig. 5(a)) and an ALD Al 2 O 3 ( Fig.…”
Section: Correlation Of Interface States/border Traps and Threshold Vmentioning
confidence: 98%
“…4 14 indicates that the conventional conductance measurement could underestimate the interface states value. For this reason, two additional electrical evaluations were used: AC-g m dispersion 8,15 and the V TH shift during a positive gate bias stress. The AC transconductance (AC-g m ) technique was developed to examine the effect of border traps on the carrier transport, and it is assumed that the AC-g m dispersion reflects the border trap density in the gate dielectric.…”
Section: Correlation Of Interface States/border Traps and Threshold Vmentioning
confidence: 99%
“…In particular, Ge and III-V compounds [2] are the first candidates for p-and n-type channels respectively, although a Ge CMOS integration is also considered [3]. The development of compatible dielectric stacks (i.e., preserving carrier mobilities), is currently impeded by severe border trap charging, which induces intolerable hysteresis in the device I-V characteristics [4].…”
Section: Introductionmentioning
confidence: 99%
“…However, Ge/III-V MOS devices have been shown to have a high content of interface and oxide/border traps [5,6]. BTI and threshold instabilities in Si MOS stacks were found to be strongly related to MOS trap content [7][8][9][10].…”
Section: Introductionmentioning
confidence: 98%