Better I/O through byte-addressable, persistent memory

Condit, Jeremy; Nightingale, Edmund B.; Frost, Christopher; Ïpek, Engin; Lee, Benjamin; Burger, Doug; Coetzee, Derrick

doi:10.1145/1629575.1629589

Cited by 687 publications

(457 citation statements)

References 25 publications

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“…NV-heaps [6] provides some language level features that are not provided in FP-Heap such as safe point and garbage collection. PMFS [1], Aerie [16], BPFS [20], and SCMFS [21] all propose using file system to manage non-volatile memory. Traditional file system works well on low-speed devices.…”

Section: Related Workmentioning

confidence: 99%

Fast Persistent Heap Based on Non-Volatile Memory

Zhang

Lü

Wang

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYNew volatile memory (e.g. Phase Change Memroy) presents fast access, large capacity, byte-addressable, and non-volatility features. These features will bring impacts on the design of current software system. It has become a hot research topic of how to manage it and provide what kind of interface for upper application to use it. This paper proposes FP-Heap. FP-Heap supports direct access to non-volatile memory through a persistent heap interface. With FP-Heap, traditional persistent object systems can benefit directly from the byte-persistency of non-volatile memory. FP-Heap extends current virtual memory manager (VMM) to manage non-volatile memory and maintain a persistent mapping relationship. Also, FP-Heap offers a lightweight transaction mechanism to support atomic update of persistent data, a simple namespace to facilitate data indexing, and a basic access control mechanism to support data sharing. Compared with previous work Mnemosyne, FP-Heap achieves higher performance by its customized VMM and optimized transaction mechanism. key words: non-volatile memory, virtual memory manager, direct access

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Section: Related Workmentioning

confidence: 99%

Fast Persistent Heap Based on Non-Volatile Memory

Zhang

Lü

Wang

et al. 2017

IEICE Trans. Inf. & Syst.

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“…The average overhead of a clflush and mfence combined together is reported to be 250ns [14], which makes this approach costly, given that persistent memory access times are expected to be on the order of tens to hundreds of nanoseconds [3,4,7]. 1 The two instructions flush dirty data blocks from the CPU cache to persistent memory and wait for the completeness of all memory writes, and incur high overhead in persistent memory [10,14,32,33].…”

Section: Mitigating the Ordering Overheadmentioning

confidence: 99%

“…Several works tried to mitigate the ordering overhead in persistent memory with hardware support [10,32,33,34,35]. These can be classified into two approaches:…”

Section: Mitigating the Ordering Overheadmentioning

confidence: 99%

“…Since these technologies have low idle power, high storage density, and good scalability properties compared to DRAM [1,2], they have been regarded as potential alternatives to replace or complement DRAM as the technology used to build main memory [3,4,5,6,7,8,9]. Perhaps even more importantly, the non-volatility property of these emerging technologies promises to enable memory-level storage (i.e., persistent memory), which can store data persistently at the main memory level at low latency [10,11,12,13,14,15,16].…”

Section: Introduction Emerging Non-volatile Memory (Nvm) Technologmentioning

confidence: 99%

“…Their DRAM-comparable performance and better-than-DRAM technology-scalability, which can enable high memory capacity at low cost, make these technologies promising alternatives to DRAM [3,4,5]. As such, many recent works examined the use of these technologies as part of main memory [3,4,5,6,7,8,9,10,11,12,13,14,15,16], providing disk-like data persistence at DRAM-like latencies.…”

Section: Introduction Emerging Non-volatile Memory (Nvm) Technologmentioning

confidence: 99%

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Loose-Ordering Consistency for persistent memory

Shu

Sun

et al. 2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

123

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Abstract-Emerging non-volatile memory (NVM) technologies enable data persistence at the main memory level at access speeds close to DRAM. In such persistent memories, memory writes need to be performed in strict order to satisfy storage consistency requirements and enable correct recovery from system crashes. Unfortunately, adhering to a strict order for writes to persistent memory significantly degrades system performance as it requires flushing dirty data blocks from CPU caches and waiting for their completion at the main memory in the order specified by the program. This paper introduces a new mechanism, called Loose-Ordering Consistency (LOC), that satisfies the ordering requirements of persistent memory writes at significantly lower performance degradation than stateof-the-art mechanisms. LOC consists of two key techniques. First, Eager Commit reduces the commit overhead for writes within a transaction by eliminating the need to perform a persistent commit record write at the end of a transaction. We do so by ensuring that we can determine the status of all committed transactions during recovery by storing necessary metadata information statically with blocks of data written to memory. Second, Speculative Persistence relaxes the ordering of writes between transactions by allowing writes to be speculatively written to persistent memory. A speculative write is made visible to software only after its associated transaction commits. To enable this, our mechanism requires the tracking of committed transaction ID and support for multi-versioning in the CPU cache. Our evaluations show that LOC reduces the average performance overhead of strict write ordering from 66.9% to 34.9% on a variety of workloads.

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MBSA: a lightweight and flexible storage architecture for virtual machines

Chen

et al. 2017

Concurrency and Computation

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With the advantages of extremely high access speed, low energy consumption, nonvolatility, and byte addressability, nonvolatile memory (NVM) device has already been setting off a revolution in storage field. Conventional storage architecture needs to be optimized or even redesigned from scratch to fully explore the performance potential of NVM device. However, most previous NVM-related works only explore its low access latency and low energy consumption. Few works have been done to explore the appropriate way to use NVM device for improving virtual machine's storage performance. In this paper, we comprehensively evaluate and analyze conventional virtual machine's storage architecture. We find that, even with cutting-edge optimization technologies, virtual machine can only achieve 30% of NVM device's original performance. Based on this observation, we propose a memory bus-based storage architecture, which we named MBSA. Memory bus-based storage architecture can greatly shorten the length of virtual machine's storage input/output stack and improve NVM device's use flexibility. In addition, an efficient wear-leveling algorithm is proposed to prolong NVM device's lifespan. To evaluate the new architecture, we implement it as well as the wear-leveling algorithm on real hardware and software platform.Experimental results show that MBSA can provide a big performance improvement, about 2.55X, and the wear-leveling algorithm can efficiently balance write operations on NVM device with a negligible performance overhead (no more than 3%).

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Better I/O through byte-addressable, persistent memory

Cited by 687 publications

References 25 publications

Fast Persistent Heap Based on Non-Volatile Memory

Fast Persistent Heap Based on Non-Volatile Memory

Loose-Ordering Consistency for persistent memory

MBSA: a lightweight and flexible storage architecture for virtual machines

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