Best of both worlds: A bus enhanced NoC (BENoC)

Manevich, Ran; Walter, Isask'har; Cidon, Israel; Kolodny, Avinoam

doi:10.1109/eeei.2010.5662080

Cited by 11 publications

(17 citation statements)

References 18 publications

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“…Finally, we have implemented a two virtual network 2D mesh with a directory-based protocol, where a MoT broadcast subnetwork is added which handles broadcast request messages (2D bus). This last architecture resembles the one presented in [17] and helps to better understand the benefits of using the snoopy protocol in addition with a high throughput architecture.…”

Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

“…In [17] a low-latency low power bus connected to a conventional 2D mesh is proposed. Authors in [17] used the bus to efficiently handle broadcast and multicast messages reducing network latency. In [18], authors introduce crossbars in NoC environment and used them to implement an efficient invalidation MOESI protocol.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the networkon-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-onchip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol -and hence its resources -, and moving this complexity to the network, leads to a global decrease in power consumption meanwhile area is barely affected. Benefits of our proposal are due to the high-throughput and low delay of the network, but also due to the simplicity of the coherence protocol. The proposed network and protocol minimizes communication amongst cores when compared to traditional solutions based either on 2D-mesh topologies or in directory-based protocols.

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Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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show abstract

“…Aware of the importance of such issue, explicit support for multicast communications within conventional electronic NoCs has been widely proposed for moderately sized multiprocessors [17], [19]- [22]. Still, the scalability of these solutions in terms of performance and cost has not been discussed in the literature.…”

Section: Motivationmentioning

confidence: 99%

On the Area and Energy Scalability of Wireless Network-on-Chip: A Model-Based Benchmarked Design Space Exploration

Abadal

Iannazzo

Nemirovsky

et al. 2015

IEEE/ACM Trans. Networking

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Abstract-Networks-on-Chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is crucial to guarantee the scalability of NoCs in order to avoid communication to become the next performance bottleneck in multicore processors. Among other alternatives, the concept of Wireless Network-onChip (WNoC) has been proposed, wherein on-chip antennas would provide native broadcast capabilities leading to enhanced network performance. Since energy consumption and chip area are the two primary constraints, this work is aimed to explore the area and energy implications of scaling a WNoC in terms of (a) the number of cores within the chip, and (b) the capacity of each link in the network. To this end, an integral design space exploration is performed, covering implementation aspects (area and energy), communication aspects (link capacity) and networklevel considerations (number of cores and network architecture). The study is entirely based upon analytical models, which will allow to benchmark the WNoC scalability against a baseline NoC. Eventually, this investigation will provide qualitative and quantitative guidelines for the design of future transceivers for wireless on-chip communication.

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“…Manevich et al [31] advocate using a bus for specific purposes like DNUCA search and control signal broadcasts across the chip. Das et al [19] propose a hierarchical network with local buses connecting small sets of cores, connected in a grid.…”

Section: Related Workmentioning

confidence: 99%