On the Area and Energy Scalability of Wireless Network-on-Chip: A Model-Based Benchmarked Design Space Exploration

Abstract

Abstract-Networks-on-Chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is crucial to guarantee the scalability of NoCs in order to avoid communication to become the next performance bottleneck in multicore processors. Among other alternatives, the concept of Wireless Network-onChip (WNoC) has been proposed, wherein on-chip antennas would provide native broadcast capabilities leading to enhanced network performance. Since energy consumption and chip area are the two primary constraints, this work is aimed to explore the area and energy implications of scaling a WNoC in terms of (a) the number of cores within the chip, and (b) the capacity of each link in the network. To this end, an integral design space exploration is performed, covering implementation aspects (area and energy), communication aspects (link capacity) and networklevel considerations (number of cores and network architecture). The study is entirely based upon analytical models, which will allow to benchmark the WNoC scalability against a baseline NoC. Eventually, this investigation will provide qualitative and quantitative guidelines for the design of future transceivers for wireless on-chip communication.

Scalability of Broadcast Performance in Wireless Network-on-Chip

“…Recent survey works [40], [41] confirm that small-footprint antennas and transceivers operating at those frequencies will be available in the near future. Further, early prototypes at frequencies as high as 220 GHz have been presented [42].…”

“…We seek to cover a representative portion of the design space by testing the scalability of such configuration considering three MAC protocols, and then comparing it with that of a conventional NoC with two topologies and two router designs. NoCs based on optical waveguides or RF transmission lines could be also evaluated, but have been left out of the study due to scalability constraints in terms of laser power and design complexity [40].…”

“…To evaluate the costs of the proposed WNoC, we take base on rough but conservative scaling trends [25], [40] to extrapolate a reasonable design point from the transceiver designs proposed in [35] and outlined in Section 3.1. On the one hand, a sublinear downscaling in terms of area can be considered as a conservative rule of thumb given that passive components (e.g.…”

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

“…An effective broadcast platform is desirable in manycore environments, but costly to implement due to either issues related to the routed nature of NoCs [14], the design complexity of RF interconnects [15], or the laser power constraints and the network-level complexity of nanophotonics [16]. In WNoCs, instead, implementing a broadcast plane can be performed by simply tuning all on-chip antennas to the same transmission frequency.…”

Pulse interspersing in static multipath chip environments for Impulse Radio communications

“…However, as the technology downscaling allows the integration of more cores in the same chip, the communication demands also increase. Initial wired NoC solutions pose several challenges in terms of hardware optimization; there is an intrinsic trade off among delay, power requirements, and chip area utilization, also referred to as area overhead [2].…”