BER evaluation of a low-crosstalk silicon integrated multi-microring network-on-chip

Gambini, Fabrizio; Faralli, S.; Pintus, Paolo; Andriolli, N.; Cerutti, Isabella

doi:10.1364/oe.23.017169

Cited by 29 publications

(16 citation statements)

References 21 publications

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“…A 60 nm‐thick internal slab reduces the power consumption by about 25% with respect to the fully etched case without changing the heater resistance value. Parametric sweep of heater distance (i.e.,

w_{s l a b}

) shows that the power consumption can be further reduced to a minimum value of 42.6 mW per FSR assuming

w_{s l a b} = 0.5

µm, as shown in Figure b, which is consistent with the result in the literature …”

Section: Device Layout and Optimizationsupporting

confidence: 90%

PWM‐Driven Thermally Tunable Silicon Microring Resonators: Design, Fabrication, and Characterization

Pintus

Hofbauer

Manganelli

et al. 2019

Laser & Photonics Reviews

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Ring resonators are one of the fundamental building blocks of advanced integrated optical circuits. They find applications as nonlinear optical elements, filters, sensors, and switches among others. Here, a comprehensive optimization framework and experimental results of thermally tunable microring resonators in silicon photonics is presented, with a focus on standard silicon photonic foundry processes. In order to minimize the total power consumption, the ring resonators are tuned by applying a pulse‐width‐modulated electrical signal to the heaters. The thermal performance of integrated silicon and metal heaters are investigated and compared using an effective model validated by the measurement results. The heater power consumption is minimized by optimizing heater cross section, resistance, and metal contact configurations. Using the multiproject wafer run developed at CEA‐LETI, it is demonstrated that a metal heater provides 30% lower power consumption compared to an integrated silicon one, reaching a power consumption of 27.53 mW per free spectral range. The measurements are in excellent agreement with the theoretically predicted thermal performance, with a deviation as low as 5%. The proposed framework, supported by the experimental results, will serve as a design guideline set that can be easily adapted for other thermo‐optic switches in future silicon photonic applications.

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w_{s l a b}

) shows that the power consumption can be further reduced to a minimum value of 42.6 mW per FSR assuming

w_{s l a b} = 0.5

µm, as shown in Figure b, which is consistent with the result in the literature …”

Section: Device Layout and Optimizationsupporting

confidence: 90%

PWM‐Driven Thermally Tunable Silicon Microring Resonators: Design, Fabrication, and Characterization

Pintus

Hofbauer

Manganelli

et al. 2019

Laser & Photonics Reviews

Self Cite

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“…Fabrizio Gambini and al. proposed a photonic multi-microring NoC, which the theoretical model based on the transfer matrix method, has been validated through experimental results in terms of transmission spectra [8]. Transmissions at 10 GB/s have been assessed in terms of BER for both single-wavelength and multi-wavelength configurations.…”

Section: Related Workmentioning

confidence: 99%

“…Transmissions at 10 GB/s have been assessed in terms of BER for both single-wavelength and multi-wavelength configurations. The integrated NoC consists of 8 thermally tuned microrings coupled to a central ring, where the BER measurements show performance up to 10 −9 at 10 Gb/s with limited crosstalk and penalty (below 0.5 dB) induced by an interfering transmission [8]. Besides, many works deal with the crosstalk in the whole ONoC.…”

Section: Related Workmentioning

confidence: 99%

Detection and Monitoring Intra/Inter Crosstalk in Optical Network on Chip

Jedidi

2018

IJECE

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Multiprocessor system-on-chip (MPSoC) has become an attractive solution for improving the performance of single chip in objective to satisfy the performance growing exponentially of the computer applications as multimedia applications. However, the communication between the different processors’ cores presents the first challenge front the high performance of MPSoC. Besides, Network on Chip (NoC) is among the most prominent solution for handling the on-chip communication. Besides, NoC potential limited by physical limitation, power consumption, latency and bandwidth in the both case: increasing data exchange or scalability of Multicores. Optical communication offers a wider bandwidth and lower power consumption, based on, a new technology named Optical Network-on-Chip (ONoC) has been introduced in MPSoC. However, ONoC components induce the crosstalk noise in the network on both forms intra/inter crosstalk. This serious problem deteriorates the quality of signals and degrades network performance. As a result, detection and monitoring the impairments becoming a challenge to keep the performance in the ONoC. In this article, we propose a new system to detect and monitor the crosstalk noise in ONoC. Particularly, we present an analytic model of intra/inter crosstalk at the optical devices. Then, we evaluate these impairments in objective to present the motivation to detect and monitor crosstalk in ONoC, in which our system has the capability to detect, to localize, and to monitor the crosstalk noise in the whole network. This system offers high reliability, scalability and efficiency with time running time less than 20 ms.

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“…Different optical domains can be used for switching and multiplexing (e.g., space, time, wavelength, mode domain) and the combination to increase network scalability [5]- [7]. A control mechanism is added to ensure high network throughput, low latency and good scalability for scheduling data packets switched correctly between input and output ports in a synchronous manner [8]- [10]. Recently, many solutions have been proposed to develop and optimize optical interconnection networks from hardware implementation or software optimization.…”

Section: Introductionmentioning

confidence: 99%

Multi-Node All-Optical Interconnect Network Routing for Data-Center Parallel Computers

et al. 2019

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A multi-node all-optical interconnect network-routing architecture scheme and implementation technology are designed to improve high-speed and large-capacity data transmission in data centers. In the design of the optical interconnect routing electro-optic printed circuit board (EOPCB), the signal generated by the FPGA is directly modulated by the VCSEL arrays, and through the coupler into the parallel optical waveguide. The transmission link and optical switch are operated in optical domain. The designed optical waveguide comprises 12 waveguide arrays with the space of 250 µm. The all-optical interconnection routing system, which is based on the EOPCB high-speed chip multi-node waveguide, is designed, and a 4 × 4 EOPCB is fabricated. The performance of the waveguide and the entire optical interconnection network is tested. Based on 10 Gb/s VCSEL arrays, the optical interconnect network system can reach a bandwidth of 640 GHz for 4 × 4 networks. The best bit error rate for the switching system can reach 9.0 × 10-12 with no transmission error.

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BER evaluation of a low-crosstalk silicon integrated multi-microring network-on-chip

Cited by 29 publications

References 21 publications

PWM‐Driven Thermally Tunable Silicon Microring Resonators: Design, Fabrication, and Characterization

PWM‐Driven Thermally Tunable Silicon Microring Resonators: Design, Fabrication, and Characterization

Detection and Monitoring Intra/Inter Crosstalk in Optical Network on Chip

Multi-Node All-Optical Interconnect Network Routing for Data-Center Parallel Computers

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