Behavioral to structural translation in a bit-serial silicon compiler

Hartley, Richard; Jasica, J.R.

doi:10.1109/43.3219

Cited by 53 publications

(5 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[1][2][3][4] In this case, the switching activity of data is not occur, which is not power dissipation in CMOS circuit. However, the low power design adopts a key point to permit the minimum switching activity.…”

Section: Introductionmentioning

confidence: 92%

A New Efficient High-Level Synthesis Methodology for Lower Power Design

Lin

Yoon

2009

2009 International Conference on New Trends in Information and Service Science

View full text Add to dashboard Cite

This paper presents a new efficient highlevel synthesis methodology for low power design. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, the register allocation algorithm determines the minimum register after the life-time analysis of all variable in allocation algorithm. It is a minimum the switching activity using graph coloring technique for low power consumption.And the supply voltage is reduced a maximal using multiple voltage considering resource constraints.The proposed algorithm proves the effect through various high-level synthesis benchmark to adopt a low power scheduling and allocation algorithm considering in multiple supply voltage.

show abstract

Section: Introductionmentioning

confidence: 92%

A New Efficient High-Level Synthesis Methodology for Lower Power Design

Lin

Yoon

2009

2009 International Conference on New Trends in Information and Service Science

View full text Add to dashboard Cite

show abstract

“…Bit-serial arithmetic [33][34][35][36][37] can further reduce the silicon area of the filter designs. Figure 11 illustrates the bit-serial addition, which adds one negated input with the other input shifted by 3 bits.…”

Section: Bit-serializationmentioning

confidence: 99%

Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters

Kuo

Lin

2011

EURASIP J. Adv. Signal Process.

View full text Add to dashboard Cite

The coefficient values and number representations of digital FIR filters have significant impacts on the complexity of their VLSI realizations and thus on the system cost and performance. So, making a good tradeoff between implementation costs and quantization errors is essential for designing optimal FIR filters. This paper presents our complexity-aware quantization framework of FIR filters, which allows the explicit tradeoffs between the hardware complexity and quantization error to facilitate FIR filter design exploration. A new common subexpression sharing method and systematic bit-serialization are also proposed for lightweight VLSI implementations. In our experiments, the proposed framework saves 49% ∼ 51% additions of the filters with 2's complement coefficients and 10% ∼ 20% of those with conventional signed-digit representations for comparable quantization errors. Moreover, the bit-serialization can reduce 33% ∼ 35% silicon area for less timing-critical applications.

show abstract

“…A major challenge is to design a compiler that covers the complete trajecto O, from behavioural specification language to layout, and to demonstrate its use on applications of industrial size. A few attempts in this direction have recently triggered industrial interest [7] [4] [81 [9] [10].…”

Section: Literature Surveymentioning

confidence: 99%

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Goossens

Lanneer

Pauwels

et al. 1995

Journal of VLSI Signal Processing

View full text Add to dashboard Cite

Abstract. Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a high-level synthesis system for integration of real-time signal processing systems on such processor cores. The compiler supports a flexible architectural model. It can handle certain types of incompletely specified architectures, and offers capabilities for retargetable compilation and architectural exploration. Results for a realistic application from the domain of audio processing indicate the feasibility and power of the presented approach.

show abstract

Behavioral to structural translation in a bit-serial silicon compiler

Cited by 53 publications

References 17 publications

A New Efficient High-Level Synthesis Methodology for Lower Power Design

A New Efficient High-Level Synthesis Methodology for Lower Power Design

Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Contact Info

Product

Resources

About