Behavioral synthesis techniques for intellectual property protection

Abstract

We introduce dynamic watermarking techniques for protecting the value of intellectual property of CAD and compilation tools and reusable design components. The essence of the new approach is the addition of a set of design and timing constraints which encodes the author's signature. The constraints are selected in such a way that they result in a minimal hardware overhead while embedding a unique signature that is difficult to remove and forge. Techniques are applicable in conjunction with an arbitrary behavioral synthesis task such as scheduling, assignment, allocation, transformation, and template matching. On a large set of design examples, studies indicate the effectiveness of the new approach that results in signature data that is highly resilient, difficult to detect and remove, and yet is easy to verify and can be embedded in designs with very low hardware overhead. For example, the probability that the same design with the embedded signature is obtained by any other designers by themselves is less than 1 in 10 102 , and no register overhead was incurred. The probability of tampering, the probability that part of the embedded signature can be removed by random attempts, is shown to be extremely low, and the watermark is additionally protected from such tampering with error-correcting codes.

Netlist-level IP protection by watermarking for LUT-based FPGAs

“…It encodes an author's signature into an optimization or synthesis problem, by limiting the overall solutions space to a certain area reflecting the given signature. Approaches include only allowing a certain number of inputs to a gate [14], modification of register ordering by graph coloring [7], imposing timing constraints on nets to achieve a distinct signature in [8], and only allowing a set of standard cells the design is mapped onto [10].…”

Soft IP Protection: Watermarking HDL Codes

“…The essence of their approach is to introduce watermark-related additional constraints into the input of a black-box design tool such that the design will be rather unique and the embedded watermark can be revealed as proof of authorship. This approach is generic and has been applied to various stages of the VLSI design process, from behavioral and logic synthesis to standard cell place and route algorithms, to FPGA designs [7,8,9,10,11,14].…”

Zero overhead watermarking technique for FPGA designs

“…The protection is achieved by tracing unauthorized reuse and by making it as difficult as re-designing the IP from scratch. This approach has been applied to various aspects of the VLSI design process, from behavioral and logic synthesis to standard cell place and route algorithms, to FPGA designs [2,4,5,7,10,11]. There are also several studies on IP fingerprinting techniques [1,7,12] and methods to recover the embedded signatures [3,6,13].…”