Netlist-level IP protection by watermarking for LUT-based FPGAs

Schmid, Moritz; Ziener, Daniel; Teich, Jürgen

doi:10.1109/fpt.2008.4762385

Cited by 42 publications

(35 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This methodology can be integrated in the System-on-Chip design and manufacturing flow to simultaneously obfuscate and authenticate the design. Ziener et aL [18] proposed a novel approach that can achieve the goals of zero overhead without affecting the function and performance of design .In this method details of effectively not utilized LUTs (ILUTs) details are from post layout of FPGA design flow. Pseudo random number sequence determines the location where encrypted watermarks need to be encrypted.…”

Section: A Ip Protection At Layout Levelmentioning

confidence: 99%

A new approach to protect FPGA based sequential IP cores

Meenakumari¹,

Athisha²

2014

2014 International Conference on Electronics and Communication Systems (ICECS)

View full text Add to dashboard Cite

Protection of Intellectual property (IP) cores plays an important role in the EDA industry because a large amount of money is invested in designing IP core. IP vendors are facing major challenge to protect IPs and to prevent revenue loss due to IP piracy. In this paper a new dynamic watermarking scheme is proposed. The watermark is embedded in the state transitions of FSM at the behavioural level. A watermark is embedded into FSM by hierarchically splitting original FSM into smaller FSMs. Experimental results on IWLS93 benchmarks shows that the watermarking technique is a secure and robust method for protecting IP cores represented in FSM.

show abstract

Section: A Ip Protection At Layout Levelmentioning

confidence: 99%

A new approach to protect FPGA based sequential IP cores

Meenakumari¹,

Athisha²

2014

2014 International Conference on Electronics and Communication Systems (ICECS)

View full text Add to dashboard Cite

show abstract

“…O�i naldes�n 32 bi t watermark 256 bi t watermark 512bi 1watermark Ci rcui 1 CeUs(sli ces) Ti mi ng(lIS) iIR(%) lIT(%) iIR(%) lIT(%) iIR(%) lIT(%) In this section, the presented method is compared with methods in literature [8] and literature [11] for performance evaluation. Take MD5 core as test circuit, we sample the experiment results after embedding 32bit, 64bit, 1 28bit, 256bit and 5l 2bit watermark respectively using our method, methods in literature [8] and literature [1 1 ].…”

Section: Tabl the Change Rate Of Resource And Timing After Watermarkmentioning

confidence: 99%

“…On the basis of FPGA design flow, specific watermark could be inserted into any design level for ownership identification [4][5][6][7][8][9][11][12]. 1.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-based intellectual property protection method at physical design level

Liang

Long

Huang

et al. 2012

2012 International Conference on Computer Science and Information Processing (CSIP)

View full text Add to dashboard Cite

An FPGA-based intellectual property protection method at physical design level is presented for ownership identification in IP reuse. The method uses the special physical structure of FPGA for watermark insertion and adds corresponding checkout mechanism in functional circuit for strengthening robustness. Watermark extractor is designed for extracting watermark by analyzing bitstream. The experimental results on Xilinx Virtex II Pro XC2VP4 shows, the presented method has less resource and timing overhead.

show abstract

“…Currently there are various types of FPGA-based watermarking schemes in practise [8][9][10][11][12][13]. Further these watermarking schemes are employed at different abstraction levels of FPGA design flow like the physical design level [14][15][16][17], structural level [18][19][20][21] and behavioural level [22][23], in order to provide the required intellectual property protection of the FPGA IP cores. Also there are various fingerprinting techniques available for the FPGA IP core protection [24][25][26].…”

Section: Introductionmentioning

confidence: 99%