Behavioral model of charge pumps with VHDL

Mita, R.; Palumbo, G.; Pennisi, Marzio

doi:10.1109/icecs.2005.4633558

Cited by 4 publications

(2 citation statements)

References 15 publications

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“…Therefore, nominal values were used in the filter model. Resistor noise was implemented as voltage sources, generating a Gaussian sequence , with a variance equal to (11) where is Boltzmann's constant, is the temperature in Kelvin, is the resistance, and is the sampling frequency of the noise source. The sampling frequency is set to 10 MHz, which is sufficiently large compared to the system bandwidth of 20 kHz.…”

Section: Pll With Qss Loop-filter Models Simulation Resultsmentioning

confidence: 99%

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Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

Jakobsson

Serban

Gong

2015

IEEE Trans. Circuits Syst. I

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A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First-and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.

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Section: Pll With Qss Loop-filter Models Simulation Resultsmentioning

confidence: 99%

“…They allow analog behavioral models, i.e., models simulated using a SPICE-type analog solver, to react on digital events. This permits a more effective system-level design and verification [11]- [15]. However, there are still drawbacks to using a SPICE-type analog solver, as illustrated in the case of a 0.…”

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confidence: 99%