Modeling of Feedback Analog Circuits with VHDL

Cataldo, G. Di; Mita, R.; Palumbo, G.; Pennisi, Marzio

doi:10.1109/icecs.2006.379930

Cited by 2 publications

(6 citation statements)

References 5 publications

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“…The MixED method presented before is open to incorporate higher order device models and integration algorithms. For these purposes, one may write (1) with Laplace domain equations in the frequency domain, as demonstrated (e.g., in [18], [24], and [25]) (38) After replacing the Laplace variable by , the resulting differential equation can be integrated by using one of the implicit numerical methods (e.g., presented in [50]). …”

Section: G Higher Order Models and Integration Methodsmentioning

confidence: 99%

“…Several approaches of device and circuit modeling aiming either at feasibility [13]- [18] or simulation speed [1], [22]- [27] within an event-driven environment have been presented. In particular, the method of integrating Laplace domain equations, for example, [18], [24], and [25] permits the implementation of higher order models. Several lowand high-order integration algorithms are described in [50], together with error estimations.…”

Section: Device Modeling Examplesmentioning

confidence: 99%

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An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

Schubert

2009

IEEE Trans. Circuits Syst. I

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This paper describes a very-high-speed integrated-circuit hardware description language (VHDL)-based analog-node model, an associated driver component for the mixed-signal event-driven (MixED) simulation technique, and some primitive device models applied to radio-frequency integrated circuits. With the presented MixED method, analog circuits are modeled as a composition of controlled sources. Unlike other VHDL-based analog simulation methods, these MixED sources compute not only a real number representing an output voltage but also an output impedance. This allows the outputs of several MiXED sources to be connected in order to drive the same node signal . The voltage of this record-type signal is automatically computed at its element by resolution functions in compliance with Kirchhoff's current law. The data structure of the node signal , its self-defined resolution functions, and an associated driver component are presented and discussed to meet different simulation requirements, such as speed, versatility, current accuracy, and adaptive time stepping. Several examples demonstrate how to behaviorally model mixed-signal components with this method with an emphasis on the simulation of a heterodyne receiver. Simulation speeds are compared to VHDL-AMS tools.Index Terms-Analog, mixed signal, modeling, RF, RF integrated circuit (RFIC), simulation, system on a chip (SoC), verification, very-high-speed integrated-circuit hardware description language (VHDL).

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Section: G Higher Order Models and Integration Methodsmentioning

confidence: 99%

Section: Device Modeling Examplesmentioning

confidence: 99%

An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

Schubert

2009

IEEE Trans. Circuits Syst. I

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“…The input and output are now twoelement vectors representing the value/slope pairs and , respectively (line 7-8). The parameters and variables are the same as for the first-order version, except variables for the input and output slopes are added (line 16,18,20). 6 …”

Section: A Interface Parameter and Variable Declarationsmentioning

confidence: 99%

“…This can be realized using fixed time-step models of analog circuits [3], [16]- [18]. The drawback of this approach is that many analog signals cannot accurately be represented using fixed-step sampling.…”

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confidence: 99%

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Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

Jakobsson

Serban

Gong

2015

IEEE Trans. Circuits Syst. I

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A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First-and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.

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Modeling of Feedback Analog Circuits with VHDL

Cited by 2 publications

References 5 publications

An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

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