Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network

Abstract

Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N 3 ), and the computation complexity of prediction is O(N 2 ), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neuralnetwork-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N ) training time and constant prediction time. The efficiency of the proposed method has been verified by two realworld analog circuits.

Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process

“…in which GAIN means the open-loop gain of circuit, and UGF denotes the unity gain frequency, and PM is the phase margin. Here, for approaches other than our proposed method, we use the data in [3]. For our proposed method, the maximum number of iterations is chosen as 85 and the initial sample number is set to 30.…”

“…Analog integrated circuits are becoming more and more complex due to the development of IC technology, which makes manual analog circuit design increasingly challenging. Automated analog circuit sizing attracted many research interests [1] [2] [3] because it can be easily formulated as nonlinear optimization problem and carefully designed optimization algorithms can be performed on it.…”

“…OPTIMIZATION RESULTS OF THE TWO-STAGE OPERATIONAL AMPLIFIER, THE DATA OF WEIBO, GASPAD AND DE COME FROM[3] …”

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

“…For optimization algorithms, either evolutionary algorithms [11] and multi-start local optimization algorithms [6], [8] can be employed. Regarding surrogate modeling methods, most existing research works use the Gaussian process (GP) [16] because of its much stronger learning ability compared to other alternatives (e.g., standard artificial neural networks (ANN), radial basis functions) [8], [11], [17], [18], [19]. Therefore, typical methods for microwave analog circuit synthesis, such as GASPAD [11] and typical methods for general analog circuit sizing, such as WEIBO [8] and its improvement, employ GP.…”

“…The computational complexity is O(N it K 3 d) [20], where N it is the number of iterations spent in hyper-parameter optimization and K is the number of training data points, which is most critical and is affected by d (number of design variables) to construct a reliable surrogate model. [18], [19] propose new methods to reduce the GP training cost, which are important. However, when considering the complete set of specifications, which could be more than 20, the GP modeling may still be a burden compared to working with a few specifications.…”