BAT: The Bit-Level Analysis Tool

Manolios, Panagiotis; Srinivasan, Sudarshan K.; Vroon, Daron

doi:10.1007/978-3-540-73368-3_35

Cited by 22 publications

(15 citation statements)

References 6 publications

(10 reference statements)

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“…Boolector [3] uses bitblasting to PicoSAT with the use of under-approximation techniques that rely strongly on the connection to PicoSAT. BAT [10] also uses bit-blasting, but to an internal Boolean DAG format called NICE, from which efficient CNF generation is employed. In contrast with BAT, BEAVER uses an and-inverter graph back-end with circuit optimization techniques drawn from the logic synthesis literature, as well as offline template optimizations (described in the following section), which is an automated optimization, distinct from the use of user-defined functions in BAT.…”

Section: Related Workmentioning

confidence: 99%

“…This theory is useful for reasoning about low-level system descriptions in languages such as C and Verilog which use finite-precision integer arithmetic and bit-wise operations on bit-vectors. Recently, there has been a resurgence of work on new QF BV SMT solvers such as BAT [10], Boolector [3], MathSAT [4], Spear [9], STP [8], UCLID [5] and Z3 [6].…”

Section: Introductionmentioning

confidence: 99%

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Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic

Jha

Limaye

Seshia

2009

Computer Aided Verification

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We present the key ideas in the design and implementation of Beaver, an SMT solver for quantifierfree finite-precision bit-vector logic (QF BV). Beaver uses an eager approach, encoding the original SMT problem into a Boolean satisfiability (SAT) problem using a series of word-level and bit-level transformations. In this paper, we describe the most effective transformations, such as propagating constants and equalities at the word-level, and using and-inverter graph rewriting techniques at the bit-level. We highlight the implementation details of these transformations that distinguishes Beaver from other solvers. We present an experimental evaluation and analysis of the effectiveness of Beaver's techniques on both hardware and software benchmarks with a selection of back-end SAT solvers.Beaver is an open-source tool implemented in Ocaml, usable with any back-end SAT engine, and has a well-documented extensible code base that can be used to experiment with new algorithms and techniques.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic

Jha

Limaye

Seshia

2009

Computer Aided Verification

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“…Several different word-level formula solvers such as UCLID [2] and BAT [7] have been used for hardware verification. These procedures can in theory be used as a foundation for induction or interpolation-based unbounded property verification, but they do not provide a general way to leverage an arbitrary bit-level model checker as a back-end decision oracle.…”

Section: Related Workmentioning

confidence: 99%

“…There has been a lot of activity lately around word-level formula decision procedures such as SMT solvers [10] and reduction-based procedures like UCLID [2] and BAT [7]. However, as promising as this direction of research is, the use of these procedures for model checking is inherently restricted in that they analyze formulas rather than sequential systems.…”

Section: Introductionmentioning

confidence: 99%

A Practical Approach to Word Level Model Checking of Industrial Netlists

Bjesse

Computer Aided Verification

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Abstract. In this paper we present a word-level model checking method that attempts to speed up safety property checking of industrial netlists. Our aim is to construct an algorithm that allows us to check both bounded and unbounded properties using standard bit-level model checking methods as back-end decision procedures, while incurring minimum runtime penalties for designs that are unsuited to our analysis. We do this by combining modifications of several previously known techniques into a static abstraction algorithm which is guaranteed to produce bit-level netlists that are as small or smaller than the original bitblasted designs. We evaluate our algorithm on several challenging hardware components.

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“…For example, serious theorems (e.g., relative consistency of AC with ZF) have been mechanically verified [1], and huge improvements in the range and capacity of decision procedures (e.g., linear arithmetic, uninterpreted functions, bit-vectors, SAT solving) have been made [2][3][4][5][6]. In the hardware industry, a number of commercial tools to support formal verification have sprung up [7][8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Getting Formal Verification into Design Flow

Arvind

Dave

Katelman

Lecture Notes in Computer Science

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Abstract. The ultimate goal of formal methods is to provide assurances about the quality, performance, security, etc. of systems. While formal tools have advanced greatly over the past two decades, widespread proliferation has not yet occurred, and the full impact of formal methods is still to be realized. This paper presents some ideas on how to catalyze the growth of formal techniques in day-to-day engineering practice. We draw on our experience as hardware engineers that want to use, and have tried to use, formal methods in our own designs. The points we make probably have been made before. However we illustrate each one with concrete designs. Our examples support three major themes: (1) correctness depends highly on the application and even a collection of formal methods cannot handle the whole problem; (2) high-level design languages can facilitate the interaction between design and formal methods; and (3) formal method tools should be presented as integrated debugging aids as opposed to one requiring mastering a foreign language or esoteric concepts.

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BAT: The Bit-Level Analysis Tool

Cited by 22 publications

References 6 publications

Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic

Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic

A Practical Approach to Word Level Model Checking of Industrial Netlists

Getting Formal Verification into Design Flow

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