A Practical Approach to Word Level Model Checking of Industrial Netlists

Bjesse, Per

doi:10.1007/978-3-540-70545-1_43

Cited by 11 publications

(6 citation statements)

References 6 publications

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“…A conference version of this paper previously appeared as [2]. The present paper expands on this work in several ways.…”

mentioning

confidence: 88%

Word level bitwidth reduction for unbounded hardware model checking

Bjesse

2009

Form Methods Syst Des

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In this paper we present a word-level model checking method that attempts to speed up safety property checking of industrial netlists. Our aim is to construct an algorithm that allows us to check both bounded and unbounded properties using standard bit-level model checking methods as back-end decision procedures, while incurring minimum runtime penalties for designs that are unsuited to our analysis. We do this by combining modifications of several previously known techniques into a static abstraction algorithm which is guaranteed to produce bit-level netlists that are as small or smaller than the original bitblasted designs. We evaluate our algorithm on several challenging hardware components.Keywords Word level · Model checking · Static analysis · Formal methods IntroductionWord-level methods, which leverage design information captured at a higher level than that of individual wires and primitive gates, are the next frontier in hardware verification. At the word level, data-path elements and data packets are viewed as entities in their own right as opposed to a group of bit-level signals without any special semantics.There has been a lot of activity lately around word-level formula decision procedures such as SMT solvers [13] and reduction-based procedures like UCLID [4] and BAT [9]. However, as promising as this direction of research is, the use of these procedures for model checking is inherently restricted in that they analyze formulas rather than sequential systems. This has two consequences: First of all, sequential properties can only be checked by these procedures by relying on methods such as induction and interpolation that employ bounded checks to infer unbounded correctness. Second, these procedures do not fit into a transformation-based approach to sequential system verification [1], where sequential verification problems are iteratively simplified and processed by any of a large set of back-end model checkers. P. Bjesse ( ) Synopsys Inc., 2025 NW Cornelius Pass Rd.,

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“…A conference version of this paper previously appeared as [2]. The present paper expands on this work in several ways.…”

mentioning

confidence: 88%

Word level bitwidth reduction for unbounded hardware model checking

Bjesse

2009

Form Methods Syst Des

Self Cite

View full text Add to dashboard Cite

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“…Early on in the development of model checking, researchers recognized the importance of symmetry reduction to combat the state explosion problem [13]. Existing approaches in the hardware domain perform data symmetry reduction and data type reduction through the use of bit-width reduction preprocessing passes or syntactic restrictions such as scalarsets [8,20,28]. There have also been abstraction-refinement loop algorithms proposed to handle memory symmetries [9].…”

Section: Definition 1 a Synchronous Transition System (Sts) Is A Tupmentioning

confidence: 99%

Partial Order Reduction for Deep Bug Finding in Synchronous Hardware

Mann

Barrett

2020

Tools and Algorithms for the Construction and Analysis of Systems

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Symbolic model checking has become an important part of the verification flow in industrial hardware design. However, its use is still limited due to scaling issues. One way to address this is to exploit the large amounts of symmetry present in many real world designs. In this paper, we adapt partial order reduction for bounded model checking of synchronous hardware and introduce a novel technique that makes partial order reduction practical in this new domain. These approaches are largely automatic, requiring only minimal manual effort. We evaluate our technique on open-source and commercial packet mover circuitsdesigns containing FIFOs and arbiters.

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“…A large number of different decision procedures for SMT, called SMT solvers, have been proposed and empirical evidence, e.g., in [4,11,19], has been given that SMT solving increases efficiency in formal reasoning. Improving the performance of SMT solvers, remains an active research challenge driven by the annual SMT competitions [13].…”

Section: Introductionmentioning

confidence: 99%

metaSMT: focus on your application and not on solver integration

Riener

Haedicke

Frehse

et al. 2016

Int J Softw Tools Technol Transfer

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Many applications from artificial intelligence and formal methods use decision procedures as their core solving engines. In this context, automated reasoning based on Satisfiability (SAT) or Satisfiability Modulo Theories (SMT) is very effective. For a given application, however, selecting the best reasoning engine is a daunting task requiring first-hand experience and insight into engine-specific implementation details. Developers have to decide which concrete engine to use and how to integrate the engine into an application. Although file formats, e.g., DIMACS CNF or SMT-LIB, standardize the input of SAT and SMT solvers, not all engines provide input interfaces compliant with these standards. When following the standard, advanced (and not standardized) features of the solvers remain unused and their integration is left to the users. This work presents meta-SMT, a framework that eases the integration of existing reasoning engines into applications. Inspired by SMT-LIB, metaSMT provides a domain-specific language that allows for engine-independent programming and offers a generic interface to advanced features as an extra abstraction layer. State-of-the-art solvers for satisfiability and other theories are available via metaSMT with little programming effort. Language bindings for C++ and Python are provided. We show how metaSMT can be used as a portfolio consistency checker for SMT-LIB2 instances. The benchmark set of the category quantifier-free bit-vector theory from SMT-LIB (1.6 GB) is used for these experiments.

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A Practical Approach to Word Level Model Checking of Industrial Netlists

Cited by 11 publications

References 6 publications

Word level bitwidth reduction for unbounded hardware model checking

Word level bitwidth reduction for unbounded hardware model checking

Partial Order Reduction for Deep Bug Finding in Synchronous Hardware

metaSMT: focus on your application and not on solver integration

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