Partial Order Reduction for Deep Bug Finding in Synchronous Hardware

Abstract

Symbolic model checking has become an important part of the verification flow in industrial hardware design. However, its use is still limited due to scaling issues. One way to address this is to exploit the large amounts of symmetry present in many real world designs. In this paper, we adapt partial order reduction for bounded model checking of synchronous hardware and introduce a novel technique that makes partial order reduction practical in this new domain. These approaches are largely automatic, requiring only minimal manual effort. We evaluate our technique on open-source and commercial packet mover circuitsdesigns containing FIFOs and arbiters.

$$\mathsf {SceneChecker}$$: Boosting Scenario Verification Using Symmetry Abstractions

“…Related Work. The idea of using symmetries to accelerate verification has been exploited in a number of contexts such as probabilistic models [15,16], automata [17,18], distributed architectures [19], and hardware [20,21]. Some symmetry utilization algorithms are implemented in Murφ [22] and Uppaal [23].…”